ATMEGA644PV-10AU Atmel, ATMEGA644PV-10AU Datasheet - Page 305
ATMEGA644PV-10AU
Manufacturer Part Number
ATMEGA644PV-10AU
Description
IC MCU AVR 64K FLASH 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644PV-10AU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
10MHz
Interface Type
2-Wire/JTAG/USART
Total Internal Ram Size
4KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Cpu Speed
10MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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24.7.12
24.7.13
24.7.14
8011O–AVR–07/10
Reading the Fuse and Lock Bits
Reading the Signature Bytes
Reading the Calibration Byte
The algorithm for reading the Fuse and Lock bits is as follows (refer to
on page 300
1. A: Load Command “0000 0100”.
2. Set OE to “0”, and BS2, BS1 to “00”. The status of the Fuse Low bits can now be read at
3. Set OE to “0”, and BS2, BS1 to “11”. The status of the Fuse High bits can now be read at
4. Set OE to “0”, and BS2, BS1 to “10”. The status of the Extended Fuse bits can now be
5. Set OE to “0”, and BS2, BS1 to “01”. The status of the Lock bits can now be read at DATA
6. Set OE to “1”.
Figure 24-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
The algorithm for reading the Signature bytes is as follows (refer to
page 300
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte (0x00 - 0x02).
3. Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA.
4. Set OE to “1”.
The algorithm for reading the Calibration byte is as follows (refer to
page 300
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
4. Set OE to “1”.
DATA (“0” means programmed).
DATA (“0” means programmed).
read at DATA (“0” means programmed).
(“0” means programmed).
for details on Command and Address loading):
for details on Command and Address loading):
for details on Command loading):
Extended Fuse Byte
Fuse Low Byte
Fuse High Byte
Lock Bits
BS2
BS2
0
1
0
1
ATmega164P/324P/644P
BS1
0
1
”Programming the Flash” on
”Programming the Flash” on
”Programming the Flash”
DATA
305
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