PIC16LF877A-I/PT Microchip Technology, PIC16LF877A-I/PT Datasheet - Page 100
PIC16LF877A-I/PT
Manufacturer Part Number
PIC16LF877A-I/PT
Description
IC PIC MCU FLASH 8KX14 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF877A-I/PT
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
33
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
44TQFP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Manufacturer:
DIPTRONICS
Quantity:
30 000
Company:
Part Number:
PIC16LF877A-I/PT
Manufacturer:
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Quantity:
10 000
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PIC16LF877A-I/PTC14
Manufacturer:
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3 365
Company:
Part Number:
PIC16LF877A-I/PTC35
Manufacturer:
MICROCHI
Quantity:
46
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PIC16F87XA
9.4.7.1
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 9-18:
DS39582B-page 98
Clock Arbitration
SDA
SCL
BRG
Value
BRG
Reload
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
03h
DX
SCL deasserted but slave holds
SCL low (clock arbitration)
02h
SCL is sampled high, reload takes
place and BRG starts its count
01h
BRG decrements on
Q2 and Q4 cycles
00h (hold off)
DX-1
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count, in the
event that the clock is held low by an external device
(Figure 9-17).
SCL allowed to transition high
03h
2003 Microchip Technology Inc.
02h
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