PIC24HJ128GP510-I/PF Microchip Technology, PIC24HJ128GP510-I/PF Datasheet - Page 20

• Manufacturer Part Number: PIC24HJ128GP510-I/PF
• Description: IC PIC MCU FLASH 64KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Hr

Specifications of PIC24HJ128GP510-I/PF

• Core Size: 16-Bit
• Program Memory Size: 128KB (43K x 24)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Controller Family/series: PIC24
• No. Of I/o's: 85
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 9
• No. Of Pwm: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24H
6.5
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. The application
program then can either attempt to restart the oscillator,
or execute a controlled shutdown. The trap can be
treated as a warm Reset by simply loading the Reset
address into the oscillator fail trap vector.
DS70166A-page 18
Fail-Safe Clock Monitor (FSCM)
Preliminary
6.6
The Reset system combines all Reset sources and
controls the device Master Reset signal.
Device Reset sources include:
• POR: Power-on Reset
• BOR: Brown-out Reset
• SWR: RESET Instruction
• EXTR: MCLR Reset
• WDTR: Watchdog Timer Time-out Reset
• TRAPR: Trap Conflict
• IOPUWR: Attempted execution of an Illegal
Opcode, or Indirect Addressing, using an
Uninitialized W register
Reset System
© 2005 Microchip Technology Inc.