ATMEGA644PV-10PU Atmel, ATMEGA644PV-10PU Datasheet - Page 20

• Manufacturer Part Number: ATMEGA644PV-10PU
• Description: IC MCU AVR 64K FLASH 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644PV-10PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: 2-Wire/JTAG/SPI/USART
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 10MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3.1
8011O–AVR–07/10
Data Memory Access Times
The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the
1024/2048/4096 bytes of internal data SRAM in the ATmega164P/324P/644P are all accessible
through all these addressing modes. The Register File is described in
ter File” on page
Figure 5-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 5-3.
Address
clk
Data Memory Map for ATmega164P/324P/644P.
On-chip Data SRAM Access Cycles
Data
Data
WR
12.
CPU
RD
(1024/2048/4096 x 8)
160 Ext I/O Reg.
64 I/O Registers
Data Memory
Compute Address
Internal SRAM
32 Registers
T1
Memory Access Instruction
Address valid
ATmega164P/324P/644P
0x0000 - 0x001F
0x04FF/0x08FF/0x10FF
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
CPU
T2
cycles as described in
Next Instruction
T3
”General Purpose Regis-
Figure
5-3.
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