PIC24FJ128GA110-I/PF Microchip Technology, PIC24FJ128GA110-I/PF Datasheet - Page 52
PIC24FJ128GA110-I/PF
Manufacturer Part Number
PIC24FJ128GA110-I/PF
Description
IC PIC MCU FLASH 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA106-IPT.pdf
(14 pages)
2.PIC24FJ128GA106-IPT.pdf
(330 pages)
3.PIC24FJ128GA106-IPT.pdf
(52 pages)
4.PIC24FJ128GB110-IPF.pdf
(292 pages)
Specifications of PIC24FJ128GA110-I/PF
Core Size
16-Bit
Program Memory Size
128KB (43K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Controller Family/series
PIC24
No. Of I/o's
85
Ram Memory Size
16KB
Cpu Speed
32MHz
No. Of Timers
5
Package
100TQFP
Device Core
PIC
Family Name
PIC24
Maximum Speed
32 MHz
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
85
Interface Type
I2C/SPI/UART
On-chip Adc
16-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ128GA110-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC24FJ128GA106-IPT PDF datasheet
- PIC24FJ128GA106-IPT PDF datasheet #2
- PIC24FJ128GA106-IPT PDF datasheet #3
- PIC24FJ128GB110-IPF PDF datasheet #4
- Current page: 52 of 330
- Download datasheet (3Mb)
TABLE 4-27:
TABLE 4-28:
TABLE 4-29:
RCON
OSCCON
CLKDIV
OSCTUN
REFOCON
Legend:
Note 1:
NVMCON
NVMKEY
Legend:
Note 1:
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
Legend:
Name
Name
Name
File
File
File
2:
Addr
0760
0766
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The Reset value of the RCON register is dependent on the type of Reset event. See
The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. See
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
0770
0772
0774
0776
0778
077A
Addr
0740
074E
0742
0744
0748
SYSTEM REGISTER MAP
NVM REGISTER MAP
PMD REGISTER MAP
Bit 15
IC8MD
TRAPR
Bit 15
T5MD
ROEN
Bit 15
WR
—
ROI
—
—
—
—
—
—
IOPUWR
WREN
IC7MD
COSC2
Bit 14
DOZE2
Bit 14
T4MD
Bit 14
—
—
—
—
—
—
—
WRERR
ROSSLP
IC6MD
Bit 13
COSC1
DOZE1
Bit 13
T3MD
Bit 13
—
—
—
—
—
—
—
IC5MD
COSC0
DOZE0
ROSEL
Bit 12
Bit 12
T2MD
Bit 12
—
—
—
—
—
—
—
—
IC4MD
RODIV3
DOZEN
Bit 11
T1MD
Bit 11
Bit 11
—
—
—
—
—
—
—
—
—
CMPMD RTCCMD PMPMD
RCDIV2
RODIV2
IC3MD
NOSC2
Bit 10
Bit 10
Bit 10
—
—
—
—
—
—
—
—
IC2MD
RCDIV1
RODIV1
NOSC1
Bit 9
Bit 9
Bit 9
—
—
—
—
CM
—
—
—
Section 6.0 “Resets”
IC1MD
IC9MD
RCDIV0
RODIV0
PMSLP
NOSC0
Bit 8
Bit 8
Bit 8
—
—
—
—
—
—
I2C1MD
CRCMD
OC8MD
CLKLOCK IOLOCK
Bit 7
Bit 7
EXTR
—
—
—
Bit 7
—
—
—
—
for more information.
OC7MD
ERASE
U2MD
Bit 6
Bit 6
SWR
—
—
—
—
Bit 6
—
—
—
OC6MD
SWDTEN
Section 8.0 “Oscillator Configuration”
Bit 5
U1MD
U4MD
Bit 5
—
LOCK
TUN5
Bit 5
—
—
—
—
—
SPI2MD
OC5MD
Bit 4
Bit 4
WDTO
NVMKEY<7:0>
TUN4
—
Bit 4
—
—
—
—
—
—
—
NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000
REFOMD CTMUMD
SPI1MD
OC4MD
U3MD
Bit 3
Bit 3
SLEEP
TUN3
Bit 3
—
—
CF
—
—
OC3MD
I2C3MD
POSCEN SOSCEN OSWEN
Bit 2
Bit 2
TUN2
—
—
—
Bit 2
IDLE
—
—
for more information.
OC2MD
I2C2MD
LVDMD
Bit 1
Bit 1
TUN1
—
—
—
Bit 1
BOR
—
—
ADC1MD
SPI3MD
OC1MD
OC9MD
Bit 0
Bit 0
TUN0
Bit 0
POR
—
—
—
—
Resets
0000
Resets
Resets
0000
0000
0000
0000
0000
0000
Note 1
Note 2
0100
0000
0000
All
All
All
(1)
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