PIC18C452-I/P Microchip Technology, PIC18C452-I/P Datasheet - Page 73

• Manufacturer Part Number: PIC18C452-I/P
• Description: IC MCU OTP 16KX16 A/D 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C452-I/P

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 34
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

REGISTER 7-7:
2001 Microchip Technology Inc.
bit 7-4
bit 3
bit 2
bit 1
bit 0
PERIPHERAL INTERRUPT ENABLE REGISTER 2 (PIE2)
Unimplemented: Read as '0'
BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
LVDIE: Low Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enables the TMR3 overflow interrupt
0 = Disables the TMR3 overflow interrupt
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
bit 7
Legend:
R = Readable bit
- n = Value at POR
U-0
—
U-0
—
U-0
—
W = Writable bit
’1’ = Bit is set
U-0
—
BCLIE
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-0
LVDIE
PIC18CXX2
x = Bit is unknown
TMR3IE
R/W-0
DS39026C-page 71
CCP2IE
R/W-0
bit 0