DSPIC33FJ128GP710-I/PT Microchip Technology, DSPIC33FJ128GP710-I/PT Datasheet - Page 62
![IC DSPIC MCU/DSP 128K 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
DSPIC33FJ128GP710-I/PT
Manufacturer Part Number
DSPIC33FJ128GP710-I/PT
Description
IC DSPIC MCU/DSP 128K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
3.DSPIC33FJ64GP206-IPT.pdf
(28 pages)
4.DSPIC33FJ128MC506-IPT.pdf
(24 pages)
Specifications of DSPIC33FJ128GP710-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
100-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP710-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ12GP201-ISO PDF datasheet
- DSPIC33FJ64GP206-IPT PDF datasheet #2
- DSPIC33FJ64GP206-IPT PDF datasheet #3
- DSPIC33FJ128MC506-IPT PDF datasheet #4
- Current page: 62 of 322
- Download datasheet (5Mb)
TABLE 4-31:
TABLE 4-32:
TABLE 4-33:
TABLE 4-34:
RCON
OSCCON
CLKDIV
PLLFBD
OSCTUN
Legend:
Note
NVMCON
NVMKEY
Legend:
Note
PMD1
PMD2
PMD3
Legend:
File Name
File Name
TRISG
PORTG
LATG
ODCG
Legend:
Note
File Name
File Name
1:
2:
1:
1:
Addr
0740
0742
0744
0746
0748
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
02E4
02E6
02E8
06E4
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
Addr
Addr
0770
0772
0774
0760
0766
PORTG REGISTER MAP
SYSTEM CONTROL REGISTER MAP
NVM REGISTER MAP
PMD REGISTER MAP
TRAPR
TRISG15
ODCG15
Bit 15
LATG15
IC8MD
Bit 15
Bit 15
T5MD
T9MD
ROI
Bit 15
RG15
—
—
—
WR
—
IOPUWR
IC7MD
Bit 14
Bit 14
T4MD
T8MD
TRISG14
ODCG14
WREN
Bit 14
LATG14
Bit 14
—
—
RG14
—
COSC<2:0>
DOZE<2:0>
IC6MD
Bit 13
T3MD
T7MD
Bit 13
WRERR
Bit 13
—
—
—
TRISG13
ODCG13
LATG13
Bit 13
—
RG13
IC5MD
Bit 12
T2MD
T6MD
Bit 12
—
—
—
Bit 12
(1)
TRISG12
ODCG12
—
—
LATG12
Bit 12
RG12
IC4MD
DOZEN
Bit 11
T1MD
Bit 11
—
—
—
—
—
Bit 11
—
—
Bit 11
—
—
—
—
IC3MD
Bit 10
Bit 10
—
—
—
—
—
Bit 10
Bit 10
—
—
—
—
—
—
FRCDIV<2:0>
NOSC<2:0>
IC2MD
Bit 9
Bit 9
—
—
—
—
—
TRISG9
ODCG9
Bit 9
LATG9
Bit 9
RG9
—
—
VREGS
DCIMD
IC1MD
Bit 8
Bit 8
—
—
TRISG8
ODCG8
LATG8
Bit 8
Bit 8
RG8
—
—
CLKLOCK
I2C1MD
OC8MD
EXTR
Bit 7
PLLPOST<1:0>
Bit 7
—
TRISG7
—
ODCG7
LATG7
Bit 7
Bit 7
RG7
—
OC7MD
Bit 6
SWR
U2MD
Bit 6
TRISG6
ODCG6
LATG6
—
—
ERASE
Bit 6
—
RG6
Bit 6
SWDTEN
LOCK
OC6MD
Bit 5
U1MD
Bit 5
—
Bit 5
—
Bit 5
—
—
—
—
—
PLLDIV<8:0>
WDTO
SPI2MD
OC5MD
Bit 4
Bit 4
—
Bit 4
—
—
—
—
Bit 4
—
NVMKEY<7:0>
—
SLEEP
SPI1MD
TRISG3
ODCG3
Bit 3
OC4MD
LATG3
Bit 3
CF
RG3
Bit 3
Bit 3
—
TUN<5:0>
PLLPRE<4:0>
TRISG2
ODCG2
Bit 2
OC3MD
IDLE
LATG2
Bit 2
C2MD
RG2
—
Bit 2
Bit 2
—
NVMOP<3:0>
LPOSCEN
TRISG1
ODCG1
LATG1
OC2MD
I2C2MD
Bit 1
Bit 1
BOR
RG1
C1MD
Bit 1
Bit 1
TRISG0
ODCG0
LATG0
OSWEN
Bit 0
OC1MD
AD1MD
AD2MD
RG0
Bit 0
POR
Bit 0
Bit 0
Resets
Resets
F3CF
xxxx
xxxx
0000
Resets
Resets
xxxx
0300
3040
0030
0000
0000
0000
All
0000
0000
0000
All
All
All
(1)
(2)
(1)
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