DSPIC33FJ128GP710-I/PT Microchip Technology, DSPIC33FJ128GP710-I/PT Datasheet - Page 2
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DSPIC33FJ128GP710-I/PT
Manufacturer Part Number
DSPIC33FJ128GP710-I/PT
Description
IC DSPIC MCU/DSP 128K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
3.DSPIC33FJ64GP206-IPT.pdf
(28 pages)
4.DSPIC33FJ128MC506-IPT.pdf
(24 pages)
Specifications of DSPIC33FJ128GP710-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
100-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP710-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
TABLE 1:
TABLE 2:
DS80446D-page 2
dsPIC33FJ128GP708
dsPIC33FJ128GP710
dsPIC33FJ256GP506
dsPIC33FJ256GP510
dsPIC33FJ256GP710
Note 1:
Note 1:
Compare
Module
Output
ECAN
ECAN
ECAN
Mode
I
Doze
ADC
ADC
CPU
CPU
2
SPI
SPI
SPI
C™
2:
The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for detailed information on
Device and Revision IDs for your specific device.
Only those issues indicated in the last column apply to the current silicon revision.
Part Number
Transmission
Transmission
Master Mode
Bus Collision
Slave Select
12-bit Mode
10-bit Mode
PWM Mode
Instruction
Instruction
Loopback
Sampling
Feature
SILICON DEVREV VALUES (CONTINUED)
SILICON ISSUE SUMMARY
Frame
Mode
EXCH
DISI
Data
Data
—
Number
Item
10.
12.
13.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
When Doze mode is enabled, any writes to a peripheral SFR
can cause other updates to that register to cease to function
for the duration of the current CPU clock cycle.
For this revision of silicon, the 12-bit ADC module INL, DNL
and signal acquisition time parameters are not within the
published data sheet specification
For this revision of silicon, the 10-bit ADC module DNL,
conversion speed and signal acquisition time parameters are
not within the published data sheet specifications.
The EXCH instruction does not execute correctly.
The DISI instruction will not disable interrupts if a DISI
instruction is executed in the same instruction cycle that the
DISI counter decrements to zero.
The output compare module will miss one compare event
when the duty cycle register value is updated from 0x0000 to
0x0001.
The SPI module will fail to generate frame synchronization
pulses in Frame Master mode.
The SPI module slave select functionality will not work
correctly.
The SMP bit does not have any effect when the SPI module is
configured for a 1:1 prescale factor in Master mode.
ECAN transmissions may be incorrect if any buffers other than
Buffer 0 are enabled as transmit buffers.
Under specific conditions, the first five bits of a transmitted
identifier may not match the value in the transmit buffer ID
register.
The ECAN module (ECAN1 or ECAN2) does not function
correctly in Loopback mode.
The Bus Collision Status bit does not get set when a bus
collision occurs during a Restart or Stop event.
Device ID
0x00EE
0x00EF
0x00F5
0x00F7
0x00FF
(1)
Issue Summary
Revision ID for Silicon Revision
0x3002
A2
© 2010 Microchip Technology Inc.
0x3004
A3
Revisions
A2 A3 A4
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
0x3040
X
X
X
X
X
X
X
X
X
X
X
X
X
A4
(2)
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)