PIC16C76-20I/SP Microchip Technology, PIC16C76-20I/SP Datasheet - Page 24
![IC MCU OTP 8KX14 A/D PWM 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16C76-20I/SP
Manufacturer Part Number
PIC16C76-20I/SP
Description
IC MCU OTP 8KX14 A/D PWM 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C63A-04SP.pdf
(184 pages)
4.PIC16C72-04SO.pdf
(289 pages)
5.PIC16C76-04SP.pdf
(8 pages)
Specifications of PIC16C76-20I/SP
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
OTP
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC16C
No. Of I/o's
22
Ram Memory Size
368Byte
Cpu Speed
10MHz
No. Of Timers
3
Interface
I2C, SPI, USART
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Package
28SPDIP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
22
Interface Type
I2C/SPI/USART
On-chip Adc
5-chx8-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16C63A-04SP PDF datasheet #3
- PIC16C72-04SO PDF datasheet #4
- PIC16C76-04SP PDF datasheet #5
- Current page: 24 of 184
- Download datasheet (3Mb)
PIC16C63A/65B/73B/74B
4.2.2.6
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
REGISTER 4-6:
4.2.2.7
This register contains the CCP2 interrupt flag bit.
REGISTER 4-7:
DS30605C-page 24
bit 7-1
bit 0
bit 7-1
bit 0
PIE2 Register
PIR2 Register
PIE2 REGISTER (ADDRESS 8Dh)
PIR2 REGISTER (ADDRESS 0Dh)
Unimplemented: Read as '0'
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit
-n = Value at POR
Unimplemented: Read as '0'
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 7
U-0
U-0
—
—
U-0
U-0
—
—
W = Writable bit
’1’ = Bit is set
W = Writable bit
’1’ = Bit is set
U-0
U-0
—
—
U-0
U-0
—
—
Note:
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt
U-0
U-0
—
—
.
U-0
U-0
—
—
2000 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
U-0
U-0
—
—
CCP2IE
CCP2IF
R/W-0
R/W-0
bit 0
bit 0
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