DSPIC33FJ256GP510A-I/PF Microchip Technology, DSPIC33FJ256GP510A-I/PF Datasheet - Page 341

• Manufacturer Part Number: DSPIC33FJ256GP510A-I/PF
• Description: IC MCU 16BIT 256KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ256GP510A-I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 85
• Flash Memory Size: 256KB
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Package: 100TQFP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 85
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 32-chx10-bit|32-chx12-bit
• Number Of Timers: 9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision C (March 2011)
This revision includes typographical and formatting
changes throughout the data sheet text. In addition, all
instances of V
All other major changes are referenced by their
respective section in the following table.
TABLE B-2:
© 2011 Microchip Technology Inc.
Section 2.0 “Guidelines for Getting Started
with 16-Bit Digital Signal Controllers”
Section 4.0 “Memory Organization”
Section 9.0 “Oscillator Configuration”
Section 21.0 “10-Bit/12-Bit
Analog-to-Digital Converter (ADC)”
Section 22.0 “Special Features”
DDCORE
Section Name
MAJOR SECTION UPDATES
have been removed.
dsPIC33FJXXXGPX06A/X08A/X10A
Updated the title of
Connection
The frequency limitation for device PLL start-up conditions was
updated in
Start-up”.
The second paragraph in
The All Resets values for the following SFRs in the Timer Register
Map were changed (see
• TMR1
• TMR2
• TMR3
• TMR4
• TMR5
• TMR6
• TMR7
• TMR8
• TMR9
Added Note 3 to the OSCCON: Oscillator Control Register (see
Register
Added Note 2 to the CLKDIV: Clock Divisor Register (see
Register
Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see
Register
Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see
Register
Updated the V
(see
Added a new paragraph and removed the third paragraph in
Section 22.1 “Configuration
Added the column “RTSP Effects” to the Configuration Bits
Descriptions (see
Figure
9-1).
9-2).
9-3).
9-4).
Section 2.7 “Oscillator Value Conditions on Device
21-1).
(Vcap)”.
REFL
Table
Section 2.3 “CPU Logic Filter Capacitor
references in the ADC1 module block diagram
Update Description
22-2).
Table
Section 2.9 “Unused I/Os”
Bits”.
4-6):
DS70593C-page 341
was updated.