PIC16LF874-04/PQ Microchip Technology, PIC16LF874-04/PQ Datasheet - Page 103
![IC PIC MCU FLASH 4KX14 44MQFP](/photos/6/59/65984/150-44-pqfp_sml.jpg)
PIC16LF874-04/PQ
Manufacturer Part Number
PIC16LF874-04/PQ
Description
IC PIC MCU FLASH 4KX14 44MQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F873-04SO.pdf
(218 pages)
Specifications of PIC16LF874-04/PQ
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-MQFP, 44-PQFP
Core
PIC
Processor Series
PIC16LF
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Data Ram Size
192 B
Data Rom Size
128 B
On-chip Adc
8
Number Of Programmable I/os
33
Number Of Timers
3 bit
Operating Supply Voltage
2 V to 5.5 V
Mounting Style
SMD/SMT
Height
2 mm
Interface Type
MSSP, PSP, USART
Length
10 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
10 mm
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF874-04/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
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10.2.2
The receiver block diagram is shown in Figure 10-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter, operating at x16 times the
baud rate; whereas, the main receive serial shifter
operates at the bit rate or at F
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled
(PIE1<5>). Flag bit RCIF is a read only bit, which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register (i.e., it is a two deep FIFO). It
FIGURE 10-4:
2001 Microchip Technology Inc.
by
F
USART ASYNCHRONOUS
RECEIVER
RC7/RX/DT
OSC
setting/clearing
Baud Rate Generator
x64 Baud Rate CLK
USART RECEIVE BLOCK DIAGRAM
SPBRG
Pin Buffer
and Control
SPEN
OSC
.
enable
bit
Data
Recovery
Interrupt
RCIE
or
64
16
CREN
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the STOP bit of the third byte, if the RCREG register is
still full, the overrun error bit OERR (RCSTA<1>) will be
set. The word in the RSR will be lost. The RCREG reg-
ister can be read twice to retrieve the two bytes in the
FIFO. Overrun bit OERR has to be cleared in software.
This is done by resetting the receive logic (CREN is
cleared and then set). If bit OERR is set, transfers from
the RSR register to the RCREG register are inhibited,
and no further data will be received. It is therefore,
essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a STOP bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore, it is essential for the user to read the
RCSTA register before reading the RCREG register in
order not to lose the old FERR and RX9D information.
RCIF
RCIE
RX9
MSb
STOP
RX9D
(8) 7
OERR
RCREG Register
RSR Register
8
Data Bus
PIC16F87X
1
FERR
0
START
DS30292C-page 101
FIFO
LSb
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