PIC18LF2585-I/SO Microchip Technology, PIC18LF2585-I/SO Datasheet - Page 4
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PIC18LF2585-I/SO
Manufacturer Part Number
PIC18LF2585-I/SO
Description
IC MCU FLASH 24KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4585-IPT.pdf
(482 pages)
4.PIC18F4585-IPT.pdf
(14 pages)
5.PIC18F4585-IPT.pdf
(8 pages)
6.PIC18F4585-IPT.pdf
(12 pages)
7.PIC18F4585-IPT.pdf
(4 pages)
Specifications of PIC18LF2585-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18LF2585-I/SOR
PIC18LF2585-I/SOR
PIC18LF2585-I/SOR
PIC18F2585/2680/4585/4680
14. Module: MSSP
15. Module: MSSP
16. Module: DC Characteristics (BOR)
17. Module: BOR/HLVD
DS80202G-page 4
RCEN becomes set when the system is idle. In
normal operation, the setting of RCEN should be
ignored by the module while the system is not idle.
Work around
Wait for the system to become idle. This requires
a check for the following bits to be reset:
ACKEN, RCEN, PEN, RSEN and SEN.
Date Codes that pertain to this issue:
All engineering and production devices.
In SPI mode, the SDO output may change after the
inactive clock edge of the bit ‘0’ output. This may
affect some SPI components that read data over
300 ns after the inactive edge of SCK.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
The values for parameter D005 (V
Section 27.1
Voltage” of the Device Data Sheet, when the trip
point for BORV1:BORV0 = 11, are not applicable
as the device may reset below the minimum
operating voltage for the device.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
Due to production tolerances, selecting the lowest
setting for Brown-out Reset (BORV1:BORV0 = 11)
or Low-Voltage Reset (LVV = 0000) is not recom-
mended, since it may result in an actual Brown-out
Reset or Low-Voltage Detect below the minimum
allowable V
Work around
Use the next highest BOR or HLVD voltage thresh-
old to ensure a low V
below 2.0V.
Date Codes that pertain to this issue:
All engineering and production devices.
DD
of 2.0V.
“DC
DD
Characteristics:
is detected before it drops
BOR
Supply
) in
18. Module: ECCP
When operating either Timer1 or Timer3 as a
counter, with a prescale value other than 1:1, and
operating the ECCP in Compare mode, with the
Special
CCP1M3:CCP1M0 = 1011), the Special Event
Trigger Reset of the timer occurs as soon as there
is
CCPR1H:CCPR1L.
This differs from the PIC18F458, where the Special
Event Trigger Reset of the timer occurs on the next
rollover of the prescale counter, after the match
between TMRxH:TMRxL and CCPR1H:CCPR1L.
Work around
To achieve the same timer Reset period on the
PIC18F4680 family as the PIC18F458 family for a
given clock source, add 1 to the value in
CCPR1H:CCPR1L.
In other words, if CCPR1H:CCPR1L = x for the
PIC18F458, to achieve the same Reset period on
the PIC18F4680 family, CCPR1H:CCPR1L = x + 1,
where the prescale is 1, 2, 4 or 8 depending on the
T1CKPS1:T1CKPS0 bit values.
Date Codes that pertain to this issue:
All engineering and production devices
a
match
Event
between
© 2007 Microchip Technology Inc.
Trigger
TMRxH:TMRxL
(CCP1CON
and
bits