PIC16LF874-04/PT Microchip Technology, PIC16LF874-04/PT Datasheet - Page 26
![IC PIC MCU FLASH 4KX14 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC16LF874-04/PT
Manufacturer Part Number
PIC16LF874-04/PT
Description
IC PIC MCU FLASH 4KX14 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F873-04SO.pdf
(218 pages)
Specifications of PIC16LF874-04/PT
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F87X
2.2.2.7
The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt and the
EEPROM write operation interrupt.
REGISTER 2-7:
DS30292C-page 24
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
bit 0
PIR2 Register
PIR2 REGISTER (ADDRESS 0Dh)
bit 7
Unimplemented: Read as '0'
Reserved: Always maintain this bit clear
Unimplemented: Read as '0'
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP, when configured for I2C Master mode
0 = No bus collision has occurred
Unimplemented: Read as '0'
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused
Legend:
R = Readable bit
- n = Value at POR
U-0
—
Reserved
R/W-0
U-0
—
W = Writable bit
’1’ = Bit is set
R/W-0
EEIF
.
Note:
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-0
BCLIF
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0
—
2001 Microchip Technology Inc.
x = Bit is unknown
U-0
—
CCP2IF
R/W-0
bit 0
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