PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 49

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 4-17:
BF88_60C0
BF88_60D0
Legend:
Note
BF88_6060
BF88_6070 ODCB
BF88_6080
BF88_6090
BF88_60A0
BF88_60B0
BF88_60E0
BF88_60F0
BF88_6100
BF88_6110
BF88_6120
Virtual
Addr
SFR
1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
11:
LATB
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TRISA, PORTA, LATA and ODCA registers are not implemented on 64-pin devices, and read as ‘0’.
JTAG program/debug port is multiplexed with port pins RA0, RA1, RA4 and RA5 on 100-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.
On specific 100-pin devices, the instruction TRACE port is multiplexed with PORTA pins RA6, RA7; PORTG pins RG12, RG13 and RG14. At Power-on Reset, these pins are general purpose I/O pins. To maintain
these pins as general purpose I/O pins, the user’s application code must maintain TROEN (DDPCON<2>) bit = 0. To use these pins as instruction TRACE pins, TROEN must be set = 1.
JTAG program/debug port is multiplexed with port pins RB10, RB11, RB12 and RB13 on 64-pin devices. At power-on-reset, these pins are controlled by the JTAG port. To use these pins for general purpose I/O, the
user’s application code must clear JTAGEN (DDPCON<3>) bit = 0. To use these pins for JTAG program/debug, the user’s application code must maintain JTAGEN bit = 1.
Port Pin RB3 is not available as a general purpose I/O pin when the USB module is enabled.
Not implemented on 64-pin devices. Read as ‘0’.
Not implemented on 64-pin USB devices. Read as ‘0’.
Not implemented on 100-pin USB devices. Read as ‘0’.
Not available as a general purpose I/O pin when USB module is enabled.
Not available as a general purpose I/O pin when USB module is enabled. Input only when the USB module is disabled.
All registers in this table have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more infor-
mation.
PORTC
PORTD
PORTE
Name
TRISC
ODCC
TRISD
ODCD
TRISE
LATC
LATD
LATE
SFR
(4,5)
(4,5)
PORT A-G REGISTERS MAP
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0 TRISD15
15:0
15:0
15:0 ODCD15
15:0
15:0
15:0
TRISC15
ODCC15
LAT15
LATC15
RD15
31/15
RC15
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(6)
(6)
(6)
(6)
TRISD14
ODCD14
TRISC14
ODCC14
LAT14
LATC14
RD14
30/14
RC14
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(6)
(6)
(6)
(6)
TRISD13
ODCD13
TRISC13
ODCC13
LAT13
LATC13
RD13
29/13
RC13
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(6)
(6)
(6)
(6)
TRISD12
ODCD12
TRISC12
ODCC12
LAT12
(11)
LATC12
RD12
28/12
RC12
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(CONTINUED)
(6)
(6)
(6)
(6)
27/11
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26/10
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISD<11:8>
ODCD<11:8>
LATD<11:8>
RD<11:8>
TRISE9
LATE9
RE9
25/9
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(6)
(6)
(6)
TRISE8
LATE8
RE8
Bits
24/8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ODCB<15:0>
LATB<15:0>
(6)
(6)
(6)
Bits
23/7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits
22/6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISC4
ODCC4
LATC4
RC4
20/4
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISD<7:0>
ODCD<7:0>
TRISE<7:0>
LATD<7:0>
LATE<7:0>
(6)
RD<7:0>
RE<7:0>
(6)
(6)
(6)
TRISC3
ODCC3
LATC3
RC3
19/3
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
(6)
(6)
(6)
(6)
TRISC2
ODCC2
LATC2
RC2
18/2
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
(6)
(6)
(6)
(6)
TRISC1
ODCC1
LATC1
RC1
Bits
17/1
—
—
—
—
—
—
—
—
—
—
—
—
—
(6)
(6)
(6)
(6)
Bits
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—