PIC16LF874-04I/L Microchip Technology, PIC16LF874-04I/L Datasheet - Page 54
![IC MCU FLASH 4KX14 EE A/D 44PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC16LF874-04I/L
Manufacturer Part Number
PIC16LF874-04I/L
Description
IC MCU FLASH 4KX14 EE A/D 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F873-04SO.pdf
(218 pages)
Specifications of PIC16LF874-04I/L
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16LF874-04I/LR
PIC16LF874-04I/LR
PIC16LF874-04I/LR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF874-04I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC16F87X
6.1
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is F
(T1CON<2>) has no effect, since the internal clock is
always in sync.
FIGURE 6-1:
6.3
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
FIGURE 6-2:
DS30292C-page 52
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
Timer1 Operation in Timer Mode
Timer1 Operation in Synchronized
Counter Mode
OSC
/4. The synchronize control bit T1SYNC
Set Flag bit
TMR1IF on
Overflow
TIMER1 INCREMENTING EDGE
TIMER1 BLOCK DIAGRAM
(2)
TMR1H
T1OSC
TMR1
TMR1L
Oscillator
Enable
T1OSCEN
(1)
Clock
Internal
F
OSC
/4
TMR1ON
6.2
Timer1 may operate in either a Synchronous, or an
Asynchronous mode, depending on the setting of the
TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple-counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
On/Off
TMR1CS
1
0
Timer1 Counter Operation
T1CKPS1:T1CKPS0
T1SYNC
Prescaler
1, 2, 4, 8
0
1
2
2001 Microchip Technology Inc.
Synchronized
Clock Input
Synchronize
Q Clock
det
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