PIC16LF874-04I/PQ Microchip Technology, PIC16LF874-04I/PQ Datasheet - Page 40
![IC PIC MCU FLASH 4KX14 44MQFP](/photos/6/59/65984/150-44-pqfp_sml.jpg)
PIC16LF874-04I/PQ
Manufacturer Part Number
PIC16LF874-04I/PQ
Description
IC PIC MCU FLASH 4KX14 44MQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F873-04SO.pdf
(218 pages)
Specifications of PIC16LF874-04I/PQ
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-MQFP, 44-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Price
Company:
Part Number:
PIC16LF874-04I/PQ
Manufacturer:
Microchip Technology
Quantity:
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Part Number:
PIC16LF874-04I/PQ
Manufacturer:
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PIC16F87X
3.6
The Parallel Slave Port (PSP) is not implemented on
the PIC16F873 or PIC16F876.
PORTD operates as an 8-bit wide Parallel Slave Port or
microprocessor port, when control bit PSPMODE
(TRISE<4>) is set. In Slave mode, it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD and WR control input pin
RE1/WR.
The PSP can directly interface to an 8-bit microproces-
sor data bus. The external microprocessor can read or
write the PORTD latch as an 8-bit latch. Setting bit
PSPMODE enables port pin RE0/RD to be the RD
input, RE1/WR to be the WR input and RE2/CS to be
the CS (chip select) input. For this functionality, the cor-
responding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set). The
A/D
(ADCON1<3:0>) must be set to configure pins
RE2:RE0 as digital I/O.
There are actually two 8-bit latches: one for data out-
put, and one for data input. The user writes 8-bit data
to the PORTD data latch and reads data from the port
pin latch (note that they have the same address). In this
mode, the TRISD register is ignored, since the external
device is controlling the direction of data flow.
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), the Input Buffer Full
(IBF) status flag bit (TRISE<7>) is set on the Q4 clock
cycle, following the next Q2 cycle, to signal the write is
complete (Figure 3-10). The interrupt flag bit PSPIF
(PIR1<7>) is also set on the same Q4 clock cycle. IBF
can only be cleared by reading the PORTD input latch.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared immedi-
ately (Figure 3-11), indicating that the PORTD latch is
waiting to be read by the external bus. When either the
CS or RD pin becomes high (level triggered), the inter-
rupt flag bit PSPIF is set on the Q4 clock cycle, follow-
ing the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
DS30292C-page 38
port
Parallel Slave Port
configuration
bits
PCFG3:PCFG0
When not in PSP mode, the IBF and OBF bits are held
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
FIGURE 3-9:
One bit of PORTD
Note 1: I/O pins have protection diodes to V
Data Bus
PSPIF(PIR1<7>)
Set Interrupt Flag
WR
Port
RD
Port
Q
D
CK
EN
EN
Q
D
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)
2001 Microchip Technology Inc.
Chip Select
Read
Write
TTL
DD
TTL
TTL
TTL
and V
SS
.
RDx
pin
CS
WR
RD
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