PIC18LF458-I/L Microchip Technology, PIC18LF458-I/L Datasheet

PIC18LF458-I/L

Manufacturer Part Number

PIC18LF458-I/L

Description

IC MCU CAN FLASH 16K LP 44-PLCC

Manufacturer

Microchip Technology

Series

PIC® 18Fr

Datasheets

1.PIC16F616T-ISL.pdf (8 pages)

2.PIC18LF242-ISO.pdf (36 pages)

3.PIC18F248-ISO.pdf (402 pages)

4.PIC18F248-ISO.pdf (8 pages)

Specifications of PIC18LF458-I/L

Core Size

8-Bit

Program Memory Size

32KB (16K x 16)

Oscillator Type

External

Core Processor

PIC

Speed

40MHz

Connectivity

CAN, I²C, SPI, UART/USART

Peripherals

Brown-out Detect/Reset, LVD, POR, PWM, WDT

Number Of I /o

Program Memory Type

FLASH

Eeprom Size

256 x 8

Ram Size

1.5K x 8

Voltage - Supply (vcc/vdd)

2 V ~ 5.5 V

Data Converters

A/D 8x10b

Operating Temperature

-40°C ~ 85°C

Package / Case

44-PLCC

Controller Family/series

PIC18

No. Of I/o's

Eeprom Memory Size

256Byte

Ram Memory Size

1536Byte

Cpu Speed

40MHz

No.

RoHS Compliant

Processor Series

PIC18LF

Core

PIC

Data Bus Width

8 bit

Data Ram Size

1.5 KB

Interface Type

SPI, I2C, USART

Maximum Clock Frequency

40 MHz

Number Of Programmable I/os

Number Of Timers

4 bit

Operating Supply Voltage

2 V to 5.5 V

Maximum Operating Temperature

+ 85 C

Mounting Style

SMD/SMT

3rd Party Development Tools

52715-96, 52716-328, 52717-734, 52712-325, EWPIC18

Development Tools By Supplier

PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM163011

Minimum Operating Temperature

- 40 C

On-chip Adc

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

PIC18LF458-I/L

Manufacturer:

Microchip Technology

Quantity:

10 000

Company:

Meier Automation Equipment Co., Limited

Part Number:

PIC18LF458-I/L

Manufacturer:

MICRCOHI

Quantity:

20 000

Current page: 1 of 8
Download datasheet (197Kb)

The PIC18FXX8 Rev. B4 parts you have received

conform functionally to the Device Data Sheet

(DS41159D), except for the anomalies described

below.

All of the issues listed here will be addressed in future

revisions of the PIC18FXX8 silicon.

The

PIC18FXX8 devices with these Device/Revision

IDs:

1. Module: ECCP

The Device IDs (DEVID1 and DEVID2) are located at

addresses

configuration space. They are shown in hexadecimal

in the format “DEVID2 DEVID1”.

Part Number

PIC18F248

PIC18F258

PIC18F448

PIC18F458

When the ECCP module is operating in Half-

Bridge mode, use of a dead-band delay other than

zero will have the effect of introducing an

unintended pulse on the P1A and P1B signals.

Work around

Disable the dead-band delay by ensuring that the

ECCP1DEL register is set to 00h.

Date Codes that pertain to this issue:

All engineering and production devices.

following

3FFFFEh:3FFFFFh

silicon

PIC18FXX8 Rev. B4 Silicon Errata Sheet

00 1000 000

00 1000 010

00 1000 001

00 1000 011

Device ID

errata apply

Revision ID

the

00100

only

device’s

2. Module: I/O (Parallel Slave Port)

The Input Buffer Full Status bit, IBF, of the TRISE

even when the PORTE input buffer has not been

read. This will occur only when the following two

conditions occur simultaneously:

• The four Least Significant bits of the BSR

• Any instruction that contains 83h in its 8 Least

Work around

All work arounds will involve setting the contents of

BSR<3:0> to some value other than 0Fh. In

addition to those proposed below, other solutions

may exist.

1. When developing or modifying code, keep

2. If accessing a part of Bank 15 is required, and

3. If pointing the BSR to Bank 15 is unavoidable,

PIC18FXX8

and

Significant bits (i.e., register file addresses,

literal data, address offsets, etc.) is executed.

these guidelines in mind:

• Assign 12-bit addresses to all variables.

• Do not set the BSR to point to Bank 15

• Allow the assembler to manipulate the

the use of Access Banking is not possible,

consider using Indirect Addressing mode.

review the absolute file listing. Verify that no

instructions contain 83h in the 8 Least

Significant bits while the BSR points to Bank 15

(BSR = 0Fh).

This allows the assembler to know when

Access Banking can be used.

(BSR = 0Fh).

Access bit present in most instructions.

Accessing the SFRs in Bank 15 will be done

through the Access Bank. Continue to use

the BSR to select Banks 1 through 5 and

the upper half of Bank 0.

DS80134H-page 1

Related parts for PIC18LF458-I/L

PIC18LF458-I/L Summary of contents

Page 1

... Disable the dead-band delay by ensuring that the ECCP1DEL register is set to 00h. Date Codes that pertain to this issue: All engineering and production devices. © 2006 Microchip Technology Inc. PIC18FXX8 2. Module: I/O (Parallel Slave Port) The Input Buffer Full Status bit, IBF, of the TRISE register (TRISE< ...

Page 2

... Write to EEADR at least one instruction cycle before setting the RD bit. The instruction between the write to EEADR and the read can be any valid instruction, including a NOP. Date Codes that pertain to this issue: All engineering and production devices. © 2006 Microchip Technology Inc. ...

Page 3

... Work around Switch to Configuration mode instead. Wake-up from CAN bus activity will continue to work even in Configuration mode. © 2006 Microchip Technology Inc. 9. Module: MSSP (All I The Buffer Full (BF) flag bit of the SSPSTAT regis- ter (SSPSTAT<0>) may be inadvertently cleared even when the SSPBUF register has not been ...

Page 4

... Start-of-Frame (SOF) in the third bit of interframe space, and if a message to be transmitted is pending, the first five bits of the transmitted identifier may be corrupted. addresses Work around None Date Codes that pertain to this issue: All engineering and production devices. © 2006 Microchip Technology Inc. ...

Page 5

... Clarifications/Corrections to the Data Sheet: In the Device Data Sheet (DS41159D), the following clarifications and corrections should be noted. None. © 2006 Microchip Technology Inc. PIC18FXX8 DS80134H-page 5 ...

Page 6

... Added silicon issue 11 (CAN). Rev F Document (11/2004) Updated silicon issue 11 (CAN) and removed all Data Sheet Clarification issues. Rev G Document (05/2005) Added silicon issue 12 (Reset). Rev H Document (08/2006) Added silicon issue 13 (CAN). DS80134H-page 6 + and V - REF 2 C and SPI © 2006 Microchip Technology Inc. ...

Page 7

... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 8

... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2006 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-3910 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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