PIC18LF2685-I/SP Microchip Technology, PIC18LF2685-I/SP Datasheet - Page 355
![IC PIC MCU FLASH 48KX16 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF2685-I/SP
Manufacturer Part Number
PIC18LF2685-I/SP
Description
IC PIC MCU FLASH 48KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18LF2685-I/SP
Core Size
8-Bit
Program Memory Size
96KB (48K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
28
Eeprom Memory Size
1024Byte
Ram Memory Size
3328Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 355 of 484
- Download datasheet (9Mb)
24.2
For PIC18F2682/2685/4682/4685 devices, the WDT is
driven by the INTRC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits (OSCCON<6:4>) are changed or a clock
failure has occurred.
.
FIGURE 24-1:
© 2009 Microchip Technology Inc.
Change on IRCF bits
All Device Resets
INTRC Source
Watchdog Timer (WDT)
WDTPS<3:0>
SWDTEN
WDTEN
CLRWDT
Sleep
WDT BLOCK DIAGRAM
Enable WDT
WDT Counter
÷128
PIC18F2682/2685/4682/4685
INTRC Control
4
Programmable Postscaler
1:1 to 1:32,768
24.2.1
Register 24-14 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
Note 1: The CLRWDT and SLEEP instructions
2: Changing the setting of the IRCF bits
3: When a CLRWDT instruction is executed,
WDT
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
(OSCCON<6:4>) clears the WDT and
postscaler counts.
the postscaler count will be cleared.
Reset
DS39761C-page 355
Wake-up from
Power-Managed
Modes
WDT
Reset
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