DSPIC30F6012A-30I/PT Microchip Technology, DSPIC30F6012A-30I/PT Datasheet - Page 233

• Manufacturer Part Number: DSPIC30F6012A-30I/PT
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 144KB (48K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F6012A30IP

SPI Module ......................................................................... 91
STATUS Register ............................................................... 16
Symbols used in Opcode Descriptions ............................. 164
System Integration ............................................................ 143
T
Table Instruction Operation Summary ................................ 51
Temperature and Voltage Specifications
Timer1 Module .................................................................... 69
Timer2 and Timer3 Selection Mode .................................... 88
Timer2/3 Module ................................................................. 73
Timer4/5 Module ................................................................. 79
Timing Characteristics
© 2006 Microchip Technology Inc.
Framed SPI Support ................................................... 91
Operating Function Description .................................. 91
Operation During CPU Idle Mode ............................... 93
Operation During CPU Sleep Mode............................ 93
SDOx Disable ............................................................. 91
Slave Select Synchronization ..................................... 93
SPI1 Register Map...................................................... 94
SPI2 Register Map...................................................... 94
Timing Characteristics
Timing Requirements
Word and Byte Communication .................................. 91
Register Map for dsPIC30F601xA ............................ 161
AC ............................................................................. 184
16-bit Asynchronous Counter Mode ........................... 69
16-bit Synchronous Counter Mode ............................. 69
16-bit Timer Mode....................................................... 69
Gate Operation ........................................................... 70
Interrupt....................................................................... 71
Operation During Sleep Mode .................................... 70
Prescaler..................................................................... 70
Real-Time Clock ......................................................... 71
Register Map............................................................... 72
16-bit Timer Mode....................................................... 73
32-bit Synchronous Counter Mode ............................. 73
32-bit Timer Mode....................................................... 73
ADC Event Trigger...................................................... 76
Gate Operation ........................................................... 76
Interrupt....................................................................... 76
Operation During Sleep Mode .................................... 76
Register Map............................................................... 77
Timer Prescaler........................................................... 76
Register Map............................................................... 81
ADC
Band Gap Start-up Time ........................................... 191
CAN Module I/O........................................................ 209
CLKOUT and I/O....................................................... 188
DCI Module
External Clock........................................................... 184
I
2
C Bus Data
Master Mode (CKE = 0) .................................... 199
Master Mode (CKE = 1) .................................... 200
Slave Mode (CKE = 1) .............................. 201, 203
Master Mode (CKE = 0) .................................... 199
Master Mode (CKE = 1) .................................... 201
Slave Mode (CKE = 0) ...................................... 202
Slave Mode (CKE = 1) ...................................... 204
Interrupts............................................................. 71
Oscillator Operation ............................................ 71
Low-speed (ASAM = 0, SSRC = 000) .............. 212
AC-Link Mode ................................................... 198
Multichannel, I
Master Mode ..................................................... 205
Slave Mode ....................................................... 207
2
S Modes ................................... 196
dsPIC30F6011A/6012A/6013A/6014A
Preliminary
Timing Diagrams
Timing Diagrams.See Timing Characteristics
Timing Requirements
Timing Specifications
I
Input Capture (CAPX)............................................... 194
OC/PWM Module...................................................... 195
Oscillator Start-up Timer........................................... 189
Output Compare Module .......................................... 194
Power-up Timer ........................................................ 189
Reset ........................................................................ 189
SPI Module
Type A, B and C Timer External Clock ..................... 192
Watchdog Timer (WDT)............................................ 189
CAN Bit..................................................................... 116
Frame Sync, AC-Link Start of Frame ....................... 126
Frame Sync, Multi-Channel Mode ............................ 126
I
PWM Output ............................................................... 89
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Band Gap Start-up Time........................................... 191
Brown-out Reset....................................................... 190
CAN Module I/O ....................................................... 209
CLKOUT and I/O ...................................................... 188
DCI Module
External Clock .......................................................... 185
I
I
Input Capture............................................................ 194
Oscillator Start-up Timer........................................... 190
Output Compare Module .......................................... 194
Power-up Timer ........................................................ 190
Reset ........................................................................ 190
Simple OC/PWM Mode ............................................ 195
SPI Module
Type A Timer External Clock .................................... 192
Type B Timer External Clock .................................... 193
Type C Timer External Clock.................................... 193
Watchdog Timer (WDT)............................................ 190
External Clock Requirements ................................... 185
PLL Clock ................................................................. 186
PLL Jitter .................................................................. 186
2
2
2
2
C Bus Start/Stop Bits
S Interface Frame Sync ......................................... 126
C Bus Data (Master Mode) .................................... 206
C Bus Data (Slave Mode) ...................................... 208
Master Mode..................................................... 205
Slave Mode ...................................................... 207
Master Mode (CKE = 0).................................... 199
Master Mode (CKE = 1).................................... 200
Slave Mode (CKE = 0)...................................... 201
Slave Mode (CKE = 1)...................................... 203
Not Tied to V
Not Tied to V
Tied to V
AC-Link Mode................................................... 198
Multichannel, I
Master Mode (CKE = 0).................................... 199
Master Mode (CKE = 1).................................... 201
Slave Mode (CKE = 0)...................................... 202
Slave Mode (CKE = 1)...................................... 204
DD
)...................................................... 154
DD
DD
2
S Modes................................... 197
), Case 1.................................. 154
), Case 2.................................. 155
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