PIC18C658-I/L Microchip Technology, PIC18C658-I/L Datasheet - Page 155
![IC PIC MCU OTP 16KX16 68PLCC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC18C658-I/L
Manufacturer Part Number
PIC18C658-I/L
Description
IC PIC MCU OTP 16KX16 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658-I/L
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Number Of I /o
52
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
Controller Family/series
PIC18
No. Of I/o's
52
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
3-Wire, I2C, SPI, USART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
52
Number Of Timers
4 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163007, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA18PQ640 - DEVICE ADAPT PIC18C658 64-TQFPAC174007 - MODULE SKT PROMATEII 68PLCC
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C658IL
Q1162292
Q1162292
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C658-I/L
Manufacturer:
Microchip
Quantity:
385
Company:
Part Number:
PIC18C658-I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18C658-I/L
Manufacturer:
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Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 155 of 366
- Download datasheet (7Mb)
15.4.7
A Repeated START condition occurs when the RSEN
bit (SSPCON2 register) is programmed high and the
I
bit is set, the SCL pin is asserted low. When the SCL
pin is sampled low, the baud rate generator is loaded
with the contents of SSPADD<5:0> and begins count-
ing. The SDA pin is released (brought high) for one
baud rate generator count (T
generator times out, if SDA is sampled high, the SCL
pin will be de-asserted (brought high). When SCL is
sampled high, the baud rate generator is re-loaded with
the contents of SSPADD<6:0> and begins counting.
SDA and SCL must be sampled high for one T
This action is then followed by assertion of the SDA pin
(SDA = 0) for one T
this, the RSEN bit (SSPCON2 register) will be automat-
ically cleared and the baud rate generator will not be
reloaded, leaving the SDA pin held low. As soon as a
START condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT register) will be set. The SSPIF bit
will not be set until the baud rate generator has
timed-out.
FIGURE 15-14: REPEAT START CONDITION WAVEFORM
2000 Microchip Technology Inc.
2
C logic module is in the IDLE state. When the RSEN
Note 1: If RSEN is programmed while any other
2: A bus collision during the Repeated
I
CONDITION TIMING
2
C MASTER MODE REPEATED START
event is in progress, it will not take effect.
START condition occurs if:
• SDA is sampled low when SCL goes
• SCL goes low before SDA is
from low to high.
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
Falling edge of ninth clock
BRG ,
SDA
SCL
while SCL is high. Following
BRG
End of Xmit
). When the baud rate
Write to SSPCON2
occurs here.
SDA = 1,
SCL(no change)
Advanced Information
BRG
T
SDA = 1,
SCL = 1
.
BRG
T
BRG
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional
eight bits of address (10-bit mode) or eight bits of data
(7-bit mode).
15.4.7.1
If the user writes the SSPBUF when a Repeated
START sequence is in progress, the WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note:
Sr = Repeated START
T
BRG
At completion of START bit,
hardware clear RSEN bit
Set S (SSPSTAT<3>)
WCOL Status Flag
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
and set SSPIF
Write to SSPBUF occurs here.
T
BRG
1st Bit
T
BRG
PIC18CXX8
DS30475A-page 155
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