PIC17C756A-33I/L Microchip Technology, PIC17C756A-33I/L Datasheet - Page 138
![IC MCU OTP 16KX16 A/D PWM 68PLCC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC17C756A-33I/L
Manufacturer Part Number
PIC17C756A-33I/L
Description
IC MCU OTP 16KX16 A/D PWM 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C756A-33I/L
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
50
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
Controller Family/series
PIC17
No. Of I/o's
50
Ram Memory Size
902Byte
Cpu Speed
33MHz
No. Of Timers
4
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
902 B
Interface Type
I2C, MSSP, RS- 232, SCI, SPI, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
50
Number Of Timers
4
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Package
68PLCC
Device Core
PIC
Family Name
PIC17
Maximum Speed
33 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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PIC17C7XX
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the MSSP interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 15-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
EXAMPLE 15-1:
The SSPSR is not directly readable, or writable and
can only be accessed by addressing the SSPBUF reg-
ister. Additionally, the MSSP status register (SSPSTAT)
indicates the various status conditions.
FIGURE 15-5:
DS30289B-page 138
LOOP BTFSS SSPSTAT, BF
MOVPF SSPBUF, RXDATA ; Save in user RAM
MOVFP TXDATA, SSPBUF ; New data to xmit
MOVLB 6
GOTO
LOOP
SPI Master SSPM3:SSPM0 = 00 xxb
MSb
LOADING THE SSPBUF
(SSPSR) REGISTER
SPI MASTER/SLAVE CONNECTION
PROCESSOR 1
Serial Input Buffer
Shift Register
(SSPBUF)
(SSPSR)
; Bank 6
; Has data been
;
;
;
; No
received
(transmit
complete)?
LSb
SDO
SCK
SDI
Serial Clock
15.1.2
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear bit SSPEN, re-initialize the SSPCON
registers and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. For the
pins to behave as the serial port function, some must
have their data direction bits (in the DDR register)
appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have DDRB<7> cleared
• SCK (Master mode) must have DDRB<6> cleared
• SCK (Slave mode) must have DDRB<6> set
• SS must have PORTA<2> set
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (DDR) register to the opposite value.
15.1.3
Figure 15-5 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
same Clock Polarity (CKP), then both controllers would
send and receive data at the same time. Whether the
data is meaningful (or dummy data) depends on the
application software. This leads to three scenarios for
data transmission:
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
SDO
SCK
SDI
ENABLING SPI I/O
TYPICAL CONNECTION
SPI Slave SSPM3:SSPM0 = 010 xb
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SSPBUF)
(SSPSR)
2000 Microchip Technology Inc.
LSb
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