ATMEGA128L-8AU Atmel, ATMEGA128L-8AU Datasheet - Page 102
ATMEGA128L-8AU
Manufacturer Part Number
ATMEGA128L-8AU
Description
IC AVR MCU 128K 8MHZ 3V 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA128-16AU.pdf
(26 pages)
2.ATMEGA128-16AU.pdf
(385 pages)
3.ATMEGA128-16AU.pdf
(389 pages)
Specifications of ATMEGA128L-8AU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
2-Wire/JTAG/USART
Total Internal Ram Size
4KB
# I/os (max)
53
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
8 MIPS
Eeprom Memory
4K Bytes
Input Output
53
Interface
2-Wire/JTAG/SPI/USART
Memory Type
Flash
Number Of Bits
8
Programmable Memory
128K Bytes
Timers
2-8-bit, 2-16-bit
Voltage, Range
4.5-5.5 V
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
4096Byte
Ram Memory Size
4KB
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128L-8AU
Manufacturer:
MURATA
Quantity:
120 000
Company:
Part Number:
ATMEGA128L-8AU
Manufacturer:
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Quantity:
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102
ATmega128
Table 52. Waveform Generation Mode Bit Description
Note:
• Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the output compare pin (OC0) behavior. If one or both of the
COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-
sponding to OC0 pin must be set in order to enable the output driver.
When OC0 is connected to the pin, the function of the COM01:0 bits depends on the
WGM01:0 bit setting. Table 53 shows the COM01:0 bit functionality when the WGM01:0
bits are set to a normal or CTC mode (non-PWM).
Table 53. Compare Output Mode, non-PWM Mode
Table 54 shows the COM01:0 bit functionality when the WGM01:0 bits are set to fast
PWM mode.
Table 54. Compare Output Mode, Fast PWM Mode
Note:
Table 55 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase
correct PWM mode.
Mode
COM01
0
1
2
3
COM01
0
0
1
1
0
0
1
1
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-
1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the
WGM01
(CTC0)
initions. However, the functionality and location of these bits are compatible with
previous versions of the timer.
compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode”
on page 96 for more details.
0
0
1
1
COM00
(1)
COM00
0
1
0
1
0
1
0
1
WGM00
(PWM0)
0
1
0
1
Description
Normal port operation, OC0 disconnected.
Reserved
Clear OC0 on compare match, set OC0 at TOP
Set OC0 on compare match, clear OC0 at TOP
(1)
Description
Normal port operation, OC0 disconnected.
Toggle OC0 on compare match
Clear OC0 on compare match
Set OC0 on compare match
Timer/Counter
Mode of Operation
Normal
PWM, Phase
Correct
CTC
Fast PWM
(1)
TOP
0xFF
0xFF
OCR0
0xFF
Update of
OCR0 at
Immediate
TOP
Immediate
TOP
2467M–AVR–11/04
MAX
MAX
TOV0 Flag
Set on
BOTTOM
MAX