ZLF645E0Q2064G Zilog, ZLF645E0Q2064G Datasheet - Page 81
ZLF645E0Q2064G
Manufacturer Part Number
ZLF645E0Q2064G
Description
IC MCU 64K FLASH 1K RAM 20-QFN
Manufacturer
Zilog
Series
Crimzon™ ZLFr
Specifications of ZLF645E0Q2064G
Core Processor
Z8 LXMC
Core Size
8-Bit
Speed
8MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, WDT
Number Of I /o
16
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.9 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Oscillator Type
-
Other names
269-4723
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ZLF645E0Q2064G
Manufacturer:
Maxim
Quantity:
28
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Table 36. Flash Page Select Register (FPS)
Table 37. Flash Sector Protect Register (FSEC)
PS026407-0408
Bit Position
[7]
[6:0]
Bits
Field
Reset
R/W
Address
Bits
Field
Reset
R/W
Address
Flash Sector Protect Register
SPROT7
IFEN
R/W
R/W
7
0
7
0
The Flash Sector Protect register (see
Select register. When the Flash Control register is unlocked and written with 5EH, the next
write to this address targets the Flash Sector Protect register. In all other cases, it
targets the Flash Page Select register.
This register selects which of the 8 available Flash memory sectors to be protected. The
reset state of each Sector Protect bit is an unprotected state. After a sector is protected by
setting its corresponding register bit, it cannot be unprotected (the register bit cannot be
cleared) without powering down the device.
Value
0
1
0
1
SPROT6
R/W
R/W
6
0
6
0
Description
IFEN —Information Area Enable
Operation to be performed on Flash main memory.
Operation to be performed on Flash Information Area.
PAGE —Page Select
This 7-bit field identifies the Flash main memory page for Page Erase and
Page unlocking. Program Memory Address[15:9] = PAGE[6:0].
The least significant 2 bits of Page identifies the Flash Information page for
Page Erase and Page unlocking. The upper significant bits must be logic 0’s.
SPROT5
R/W
R/W
5
0
5
0
Bank F, Register address: 02H
Bank F, Register address 02H
SPROT4
R/W
R/W
4
0
4
0
Table
SPROT3
PAGE
R/W
R/W
37) address is shared with the Flash Page
3
0
3
0
SPROT2
R/W
R/W
ZLF645 Series Flash MCUs
2
0
2
0
Flash Control Register Definitions
Product Specification
SPROT1
R/W
R/W
1
0
0
1
SPROT0
R/W
R/W
0
0
0
0
73
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