Z8F011ASB020EG Zilog, Z8F011ASB020EG Datasheet - Page 189
Z8F011ASB020EG
Manufacturer Part Number
Z8F011ASB020EG
Description
IC ENCORE XP MCU FLASH 1K 8SOIC
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F011ASB020EG.pdf
(282 pages)
Specifications of Z8F011ASB020EG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (1K x 8)
Program Memory Type
FLASH
Eeprom Size
16 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
8-SOIC (3.9mm Width)
Processor Series
Z8F011Ax
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
8
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z8F04A08100KITG, Z8F04A28100KITG, ZENETSC0100ZACG, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZAC, ZUSBSC00100ZACG
Minimum Operating Temperature
- 40 C
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4010
Z8F011ASB020EG
Z8F011ASB020EG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F011ASB020EG
Manufacturer:
Zilog
Quantity:
459
Part Number:
Z8F011ASB020EG
Manufacturer:
ZILOG
Quantity:
20 000
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- Download datasheet (4Mb)
PS022825-0908
Caution:
OCD Unlock Sequence (8-Pin Devices Only)
Breakpoints
High. Because of the open-drain nature of the DBG pin, the host can send a Serial Break to
the OCD even if the OCD is transmitting a character.
Because of pin-sharing on the 8-pin device, an unlock sequence must be performed to
access the DBG pin. If this sequence is not completed during a system reset, then the PA0/
DBG pin functions only as a GPIO pin.
The following sequence unlocks the DBG pin:
1. Hold PA2/RESET Low.
2. Wait 5ms for the internal reset sequence to complete.
3. Send the following bytes serially to the debug pin:
4. Release PA2/RESET. The PA0/DBG pin is now identical in function to that of the
Execution Breakpoints are generated using the BRK instruction (opcode
eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If Breakpoints are
enabled, the OCD enters DEBUG mode and idles the eZ8 CPU. If Breakpoints are not
enabled, the OCD ignores the BRK signal and the
instruction.
Between
in RESET nor DEBUG mode. If a device has been erased or has not yet been
programmed, all program memory bytes contain
illegal instruction, so some irregular behavior can occur before entering DEBUG mode,
and the register values after entering DEBUG mode differs from their specified reset
values. However, none of these irregularities prevent programming the Flash memory.
Before beginning system debug, it is recommended that some legal code be
programmed into the 8-pin device, and that a RESET occurs.
DBG
DBG
DBG
DBG
DBG
DBG pin on the 20-/28-pin device. To enter DEBUG mode, re-autobaud and write
80H to the OCD control register (see
←
←
←
←
←
80H (autobaud)
EBH
5AH
70H
CDH (32-bit unlock key)
Step 3
and
Step
4, there is an interval during which the 8-pin device is neither
On-Chip Debugger Commands
BRK
FFH
Z8 Encore! XP
instruction operates as an NOP
. The CPU interprets this as an
Product Specification
®
00H
On-Chip Debugger
on page 179).
F082A Series
). When the
178
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