ST7FLIT15BY1M6 STMicroelectronics, ST7FLIT15BY1M6 Datasheet - Page 81
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ST7FLIT15BY1M6
Manufacturer Part Number
ST7FLIT15BY1M6
Description
IC MCU 8BIT 4K FLASH 16-SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLIT15BY1M6.pdf
(159 pages)
Specifications of ST7FLIT15BY1M6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
11
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Controller Family/series
ST7
No. Of I/o's
13
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
5
Rohs Compliant
Yes
Processor Series
ST7FLIT1x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel
For Use With
497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
497-8245-5
ST7FLIT15BY1M6
ST7FLIT15BY1M6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
LITE TIMER (Cont’d)
11.3.4 Low Power Modes
11.3.5 Interrupts
Note: The TBxF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
They generate an interrupt if the enable bit is set in
the LTCSR1 or LTCSR2 register and the interrupt
mask in the CC register is reset (RIM instruction).
11.3.6 Register Description
LITE TIMER CONTROL/STATUS REGISTER 2
(LTCSR2)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = TB2IE Timebase 2 Interrupt enable
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
Bit 0 = TB2F Timebase 2 Interrupt Flag
This bit is set by hardware and cleared by software
Mode
SLOW
WAIT
ACTIVE HALT No effect on Lite timer
HALT
Timebase 1
Event
Timebase 2
Event
IC Event
Interrupt
7
0
Event
0
Event
TB1F
TB2F
Flag
ICF
0
Description
No effect on Lite timer
(this peripheral is driven directly
by f
No effect on Lite timer
Lite timer stops counting
Control
Enable
TB1IE
TB2IE
OSC
ICIE
0
Bit
/32)
0
from
Wait
Exit
Yes
0
Active
from
Halt
Exit
Yes
No
No
TB2IE
from
Exit
Halt
No
TB2F
0
reading the LTCSR register. Writing to this bit has
no effect.
0: No Counter 2 overflow
1: A Counter 2 overflow has occurred
LITE
(LTARR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = AR[7:0] Counter 2 Reload Value
These bits register is read/write by software. The
LTARR value is automatically loaded into Counter
2 (LTCNTR) when an overflow occurs.
LITE TIMER COUNTER 2 (LTCNTR)
Read only
Reset Value: 0000 0000 (00h)
Bits 7:0 = CNT[7:0] Counter 2 Reload Value
This register is read by software. The LTARR val-
ue is automatically loaded into Counter 2 (LTCN-
TR) when an overflow occurs.
LITE TIMER CONTROL/STATUS REGISTER
(LTCSR1)
Read / Write
Reset Value: 0x00 0000 (x0h)
Bit 7 = ICIE Interrupt Enable
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
CNT7
AR7
ICIE
7
7
7
CNT6
AR6
ICF
TIMER
CNT5
AR5
TB
AUTORELOAD
TB1IE
CNT4
AR4
CNT3
TB1F
AR3
CNT2
AR2
-
ST7LITE1xB
REGISTER
CNT1
AR1
-
81/159
CNT0
AR0
0
0
0
-
1