STM8S207C8T6 STMicroelectronics, STM8S207C8T6 Datasheet - Page 82
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STM8S207C8T6
Manufacturer Part Number
STM8S207C8T6
Description
MCU 8BIT 64K MEMORY 48-LQFP
Manufacturer
STMicroelectronics
Series
STM8Sr
Datasheet
1.STEVAL-MKI030V1.pdf
(105 pages)
Specifications of STM8S207C8T6
Mfg Application Notes
STM8S Getting Started
Core Processor
STM8
Core Size
8-Bit
Speed
24MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1.5K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.95 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
STM8
No. Of I/o's
38
Eeprom Memory Size
1.5KB
Ram Memory Size
4KB
Cpu Speed
24MHz
No. Of Timers
4
Rohs Compliant
Yes
Processor Series
STM8S20x
Core
STM8
Data Bus Width
8 bit
Data Ram Size
6 KB
Interface Type
CAN, 12C, SPI, UART
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
38
Number Of Timers
2
Operating Supply Voltage
2.95 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWSTM8
Development Tools By Supplier
STICE-SYS001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
For Use With
497-10032 - EVAL KIT MOTOR CONTROL STM8S497-10031 - EVAL KIT TOUCH SENSING STM8S497-10592 - BOARD DAUGHTER FOR STM8S207/8497-10593 - KIT STARTER FOR STM8S207/8 SER497-8506 - BOARD EVAL FOR STM8S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8951
STM8S207C8T6
STM8S207C8T6
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Company
Part Number
Manufacturer
Quantity
Price
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Electrical characteristics
10.3.9
82/105
I
Table 43.
1. f
2. Data based on standard I
3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
2
t
w(STO:STA)
Symbol
C interface characteristics
t
t
t
t
t
w(SCLH)
w(SCLL)
t
su(SDA)
t
su(STO)
t
t
t
t
su(STA)
h(SDA)
time
undefined region of the falling edge of SCL
h(STA)
r(SDA)
r(SCL)
f(SDA)
f(SCL)
MASTER
C
b
, must be at least 8 MHz to achieve max fast I
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
Repeated START condition setup time
STOP condition setup time
STOP to START condition time
(bus free)
Capacitive load for each bus line
I
2
C characteristics
2
C protocol requirement, not tested in production
Parameter
Doc ID 14733 Rev 11
2
C speed (400kHz)
Standard mode I
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
(3)
(2)
Max
1000
300
400
STM8S207xx, STM8S208xx
(2)
2
C Fast mode I
Min
100
0
1.3
0.6
0.6
0.6
0.6
1.3
(4)
(2)
Max
900
300
300
400
2
C
(3)
(2)
(1)
Unit
pF
µs
ns
µs
µs
µs