STM32F100V8T6B STMicroelectronics, STM32F100V8T6B Datasheet - Page 16
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STM32F100V8T6B
Manufacturer Part Number
STM32F100V8T6B
Description
MCU 32BIT 64K FLASH 100LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Specifications of STM32F100V8T6B
Featured Product
STM32 Value Line
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
24MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
80
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
STM32F100x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
6
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
STM32100B-EVAL
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
STM32100B-EVAL - EVAL BOARD FOR STM32F100VBT6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-10658
STM32F100V8T6B
STM32F100V8T6B
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F100V8T6B
Manufacturer:
STMicroelectronics
Quantity:
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Company:
Part Number:
STM32F100V8T6B
Manufacturer:
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STM32F100V8T6B
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Description
2.2.11
2.2.12
Note:
2.2.13
16/87
than the V
message and/or put the MCU into a safe state. The PVD is enabled by software.
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
●
●
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
Low-power modes
The STM32F100xx value line supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
●
●
●
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
MR is used in the nominal regulation mode (Run)
LPR is used in the Stop mode
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
PVD
threshold. The interrupt service routine can then generate a warning
STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Doc ID 16455 Rev 6