Z8F1622AR020SG Zilog, Z8F1622AR020SG Datasheet - Page 211
![IC ENCORE MCU FLASH 16K 64LQFP](/photos/12/15/121511/269-64-lqfp_sml.jpg)
Z8F1622AR020SG
Manufacturer Part Number
Z8F1622AR020SG
Description
IC ENCORE MCU FLASH 16K 64LQFP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F1622AR020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
64-LQFP
Processor Series
Z8F162x
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4241
Z8F1622AR020SG
Z8F1622AR020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F1622AR020SG
Manufacturer:
Zilog
Quantity:
160
Company:
Part Number:
Z8F1622AR020SG
Manufacturer:
Zilog
Quantity:
2 500
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PS019921-0308
START
DEBUG Mode
OCD Data Format
The operating characteristics of the Z8 Encore! XP
mode are:
•
•
•
•
•
Entering DEBUG Mode
The device enters DEBUG mode following any of the following operations:
•
•
•
Exiting DEBUG Mode
The device exits DEBUG mode following any of the following operations:
•
•
•
•
•
The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1 Stop bit
(see
D0
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to
execute specific instructions.
The system clock operates unless in STOP mode.
All enabled on-chip peripherals operate unless in STOP mode.
Automatically exits HALT mode.
Constantly refreshes the Watchdog Timer, if enabled.
Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface.
eZ8 CPU execution of a BRK (Breakpoint) instruction (when enabled).
If the DBG pin is Low when the device exits Reset, the On-Chip Debugger
automatically puts the device into DEBUG mode.
Clearing the DBGMODE bit in the OCD Control Register to 0.
Power-On Reset
Voltage Brownout reset
Asserting the RESET pin Low to initiate a Reset.
Driving the DBG pin Low while the device is in STOP mode initiates a system reset.
Figure
D1
38).
Figure 38. OCD Data Format
D2
D3
D4
®
D5
F64XX Series devices in DEBUG
Z8 Encore! XP
D6
Product Specification
D7
®
On-Chip Debugger
F64XX Series
STOP
197
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