Z16F3211AL20SG Zilog, Z16F3211AL20SG Datasheet - Page 333
![IC ZNEO MCU FLASH 32K 100LQFP](/photos/12/15/121532/z16f3211al20sg_sml.jpg)
Z16F3211AL20SG
Manufacturer Part Number
Z16F3211AL20SG
Description
IC ZNEO MCU FLASH 32K 100LQFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet
1.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F3211AL20SG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
Z16F3x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
2 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
76
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4568
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16F3211AL20SG
Manufacturer:
Zilog
Quantity:
557
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Table 170. Line Control Register (DBGLCR)
PS022008-0810
Table 169. Baud Rate Reload Register (DBGBR)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
Baud Rate Reload Register
Line Control Register
15
R/W
OE
The
communication stream. This register is automatically set by the Auto-Baud Detector. This
register cannot be written by the CPU when
RELOAD—This value is the baud rate reload value used to generate a bit clock. It is
calculated as
The
cannot be written by the CPU when
OE—Output enable
This bit controls the output driver. If the UART is enabled, this bit controls the output
driver during transmission only.
0 = Pin is open-drain during UART transmit. Pin behaves as an input if UART is disabled.
1 = Pin is driven during transmission if UART is enabled. Pin is an output if UART is
disabled.
7
0
14
Baud Rate Reload Register (DBGBR)
Line Control Register (DBGLCR)
13
TDH
R/W
6
0
12
RELOAD = SYSTEM CLOCK
11
HDS
R/W
5
0
10
P R E L I M I N A R Y
FF_E082-FF_E083
9
BAUD RATE
TXFC
R/W
4
OCDLOCK
0
RELOAD
FF_E084
8
0000H
controls the state of the UART. This register
R/W
is used to configure the baud rate of the serial
OCDLOCK
7
NBEN
is set.
R/W
3
0
6
x 8
is set.
5
R/W
NB
2
0
4
Product Specification
ZNEO
3
OUT
R/W
On-Chip Debugger
1
1
2
Z16F Series
1
PIN
X
R
0
0
317
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