Z16F2810AG20SG Zilog, Z16F2810AG20SG Datasheet - Page 297

• Manufacturer Part Number: Z16F2810AG20SG
• Description: IC ZNEO MCU FLASH 128K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810AG20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4535

Table 144. DMA Select Register (DAMxREQSEL)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
DMA Interrupts
DMA Request Select Register
R
7
0
DMA Bandwidth Selection
In the CPUCTL register, the DMABW mode bits set the maximum bus bandwidth the
DMA is allowed. There are four modes (For more details, refer to the ZNEO CPU User
Manual (UM0188)).
Table 143. DMA Bandwidth Selection
Each DMA has its own interrupt vector. For additional information on the interrupts, see
the interrupt section.
Interrupts occur on the following conditions:
•
•
•
CHANSTATE—Channel State 
0000 = DMA Off
0001 = Direct Mode, Waiting for End of Frame signal
Bits
00
01
10
11
Whenever a buffer is completed which has its IEOB set.
When the upper eight bits of the transfer length equal zero and the lower eight bits of
If a buffer has been terminated by a Request EOF.
the transfer length is equal to the DMAxLAR[23:16] and the DMA is in direct mode.
R
6
CHANSTATE
0
Description
DMA uses 100% of the bandwidth
DMA is allowed one transfer for each CPU operation
DMA is allowed one transfer for every two CPU operations
DMA is allowed one transfer for every three CPU
operations
FFE400H, FFE401H, FFE402H, FFE403H
Table 143
R
5
0
P R E L I M I N A R Y
lists the DMA bandwidth selection.
R
4
0
R/W
3
0
R/W
2
0
REQSEL
Product Specification
ZNEO
R/W
1
0
DMA Controller
Z16F Series
R/W
0
0
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