EZ80F91AZA50EG Zilog, EZ80F91AZA50EG Datasheet - Page 96
EZ80F91AZA50EG
Manufacturer Part Number
EZ80F91AZA50EG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91AZA50EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4563
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 30. Chip Select x Bus Mode Control Register (CS0_BMC = 00F0h, CS1_BMC =
PS027001-0707
00F1h, CS2_BMC = 00F2h, CS3_BMC = 00F3h)
Bit
CS0_BMC Reset
CS1_BMC Reset
CS2_BMC Reset
CS3_BMC Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
[7:6]
BUS_MODE
5
AD_MUX
4
Chip Select x Bus Mode Control Register
The Chip Select Bus Mode register (see
Z80, Intel™, or Motorola bus modes. Changing the bus mode allows the eZ80F91 device
to interface to peripherals based on the Z80, Intel™, or Motorola style asynchronous bus
interfaces. When a bus mode other than eZ80 is programmed for a particular chip select,
the CSx_WAIT setting in that Chip Select Control Register is ignored.
Value Description
00
01
10
11
0
1
0
R/W
eZ80
Z80 bus mode
Intel™ bus mode
Motorola bus mode
Separate address and data
Multiplexed address and data—appears on data bus
DATA[7:0]
Reserved
7
0
0
0
0
bus mode
R/W
6
0
0
0
0
R/W
5
0
0
0
0
R
4
0
0
0
0
Table
R/W
3
0
0
0
0
30) configures the chip select for eZ80,
R/W
2
0
0
0
0
R/W
1
1
1
1
1
Chip Selects and Wait States
Product Specification
R/W
0
0
0
0
0
eZ80F91 ASSP
88
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