C8051F986-GU Silicon Laboratories Inc, C8051F986-GU Datasheet - Page 2

• Manufacturer Part Number: C8051F986-GU
• Description: IC MCU 8BIT 8KB FLASH 24QSOP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F986-GU

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 24-QSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Ram Size: 512 B
• Interface Type: I2C, SMBus, Enhanced UART, Enhanced SPI
• Maximum Clock Frequency: 7 KHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Operating Supply Voltage: 2.4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F996DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 10 Channel
• On-chip Dac: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1953-5

Errata Details
1. Capacitive Sense Pin Monitor
2. CS0MD1 Bit Mapping
3. No ADC Input on P1.4
4. SmaRTClock Startup Time
5. Non Sleep Mode Current
Description: An issue has been identified with the capacitive sense pin monitor function when the device
enters Suspend mode. If the pin monitor is enabled, under some circumstances, conversions may be
continuously initiated.
Impacts: The Capacitive sense conversion may not complete due to continuously being restarted.
Workaround: Disable all pin monitor functionality (CS0PM = 0x00) before entering Suspend mode.
Resolution: Fixed in Rev B and later.
Description: Bit 4 and Bit 5 of CS0MD1 have been incorrectly mapped to Bit 5 and Bit 6.
Impacts: Both the CS0 Digital Polarity Select and the CS0 Double Reset Select function share the same bit
(Bit 5) in the CS0MD1 register. This may cause a limitation in functionality if these functions are being used.
Workaround: Since making a change to one of the functions will cause a change to the other function, care
should be taken when setting up either function. If Bit 5 and Bit 6 are not written, then the device will follow
the default behavior described in the data sheet.
Resolution: Fixed in Rev B and later.
Description: An issue has been identified that prevents P1.4 from being routed to the ADC.
Impacts: On C8051F996/7/8/9 devices, P1.4 cannot be used as an analog input for the ADC. This behavior
does not affect C8051F990/1/2/3/4/5 devices.
Resolution: Fixed in Rev B and later.
Description: A modification was made to the SmaRTClock crystal driver circuit.
Impacts: The startup time of the SmaRTClock crystal oscillator is longer than other devices in the ‘F9xx
family. Instability may occur at voltages above 3.0 V. The “Oscillator Robustness Test” described in the data
sheet is not a valid way to determine oscillator robustness for this silicon revision.
Workaround: Disable automatic gain control or use bias doubling to increase the drive current if the crystal
has high ESR (> 40 k) or if the supply voltage is greater than 3.0 V.
Resolution: Fixed in Rev B and later.
Description: An internal pull-up transistor is enabled, drawing approximately 100 µA, when the precision
oscillator is disabled.
Impacts: In all power modes other than Sleep mode, device power consumption will be 100 µA higher than
data sheet specifications if the precision oscillator is disabled.
Resolution: Fixed in Rev B and later.
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