C8051F236-GQ Silicon Laboratories Inc, C8051F236-GQ Datasheet - Page 82

• Manufacturer Part Number: C8051F236-GQ
• Description: IC 8051 MCU 8K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F2xxr

Specifications of C8051F236-GQ

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 48-TQFP, 48-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 32
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F2x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F226DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 32 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1244

C8051F2xx
82
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
PXVLD
R/W
Bit7
PXVLD: External Clock Source Valid (XTLVLD) Interrupt Priority Control.
This bit sets the priority of the XTLVLD interrupt.
0: XTLVLD interrupt set to low priority level.
1: XTLVLD interrupt set to high priority level.
Reserved. Must write 0. Reads 0.
PSCI3: Software Controlled Interrupt 3 Priority Control.
This bit sets the priority of the Software Controlled Interrupt 3.
0: External Interrupt 7 set to low priority level.
1: External Interrupt 7 set to high priority level.
PSCI2: Software Controlled Interrupt 2 Priority Control.
This bit sets the priority of the Software Controlled Interrupt 2.
0: Software Controlled Interrupt 2 set to low priority level.
1: Software Controlled Interrupt 2 set to high priority level.
PSCI1: Software Controlled Interrupt 1 Priority Control.
This bit sets the priority of the Software Controlled Interrupt 1.
0: Software Controlled Interrupt 1 set to low priority level.
1: Software Controlled Interrupt 1 set to high priority level.
PSCI0: Software Controlled Interrupt 0 Priority Control.
This bit sets the priority of the Software Controlled Interrupt 0.
0: Software Controlled Interrupt 0 set to low priority level.
1: Software Controlled Interrupt 0 set to high priority level.
PADC0: ADC End of Conversion Interrupt Priority Control.
This bit sets the priority of the ADC0 End of Conversion Interrupt.
0: ADC0 End of Conversion interrupt set to low priority level.
1: ADC0 End of Conversion interrupt set to high priority level.
Reserved. Read = 0, Write = don't care.
R/W
Bit6
-
SFR Definition 9.13. EIP2: Extended Interrupt Priority 2
PSCI3
R/W
Bit5
PSCI2
R/W
Bit4
Rev. 1.6
PSCI1
R/W
Bit3
PSCI0
R/W
Bit2
PADC0
R/W
Bit1
R/W
Bit0
-
SFR Address:
Reset Value
00000000
0xF7