C8051F715-GQ Silicon Laboratories Inc, C8051F715-GQ Datasheet - Page 172
C8051F715-GQ
Manufacturer Part Number
C8051F715-GQ
Description
IC 8051 MCU 8K FLASH 48-TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F71xr
Specifications of C8051F715-GQ
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
39
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1635 - DEV KIT FOR C8051F700
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1619
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F715-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F715-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F70x/71x
SFR Definition 27.1. CLKSEL: Clock Select
SFR Address = 0xBD; SFR Page= F
172
Name
Reset
6:4
2:0 CLKSEL[2:0] System Clock Select.
Bit
Type
7
3
Bit
Reserved
CLKRDY
CLKDIV
CLKRDY
Name
R
7
0
System Clock Divider Clock Ready Flag.
0: The selected clock divide setting has not been applied to the system clock.
1: The selected clock divide setting has been applied to the system clock.
System Clock Divider Bits.
Selects the clock division to be applied to the selected source (internal or external).
000: Selected clock is divided by 1.
001: Selected clock is divided by 2.
010: Selected clock is divided by 4.
011: Selected clock is divided by 8.
100: Selected clock is divided by 16.
101: Selected clock is divided by 32.
110: Selected clock is divided by 64.
111: Selected clock is divided by 128.
Read = 0b. Must write 0b.
Selects the oscillator to be used as the undivided system clock source.
000: Internal Oscillator
001: External Oscillator
All other values reserved.
R/W
6
0
CLKDIV[2:0]
R/W
5
0
Rev. 1.0
R/W
4
0
Reserved
Function
R
3
0
R/W
2
0
CLKSEL[2:0]
R/W
1
0
R/W
0
0
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