C8051F505-IQ Silicon Laboratories Inc, C8051F505-IQ Datasheet - Page 242

• Manufacturer Part Number: C8051F505-IQ
• Description: IC 8051 MCU 32K FLASH 48-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F505-IQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-QFP
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• Package: 48PQFP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1520

C8051F50x/F51x
242
Values Read
0100 0 0 0 A slave byte was transmitted;
0101 0 X X An illegal STOP or bus error
0010 1 0 X A slave address + R/W was
0001 0 0 X A STOP was detected while
0000 1 0 X A slave byte was received;
0010 0 1 X Lost arbitration while attempt-
0001 0 1 X Lost arbitration due to a
0000 1 1 X Lost arbitration while transmit-
0 0 1 A slave byte was transmitted;
0 1 X A Slave byte was transmitted;
1 1 X Lost arbitration as master;
1 1 X Lost arbitration while attempt-
Current SMbus State
NACK received.
ACK received.
error detected.
was detected while a Slave
Transmission was in progress.
received; ACK requested.
slave address + R/W received;
ACK requested.
addressed as a Slave Trans-
mitter or Slave Receiver.
ing a STOP.
ACK requested.
ing a repeated START.
detected STOP.
ting a data byte as master.
Table 23.4. SMBus Status Decoding
Rev. 1.2
Typical Response Options
No action required (expecting
STOP condition).
Load SMB0DAT with next data
byte to transmit.
No action required (expecting
Master to end transfer).
Clear STO.
If Write, Acknowledge received
address
If Read, Load SMB0DAT with
data byte; ACK received address
NACK received address.
If Write, Acknowledge received
address
If Read, Load SMB0DAT with
data byte; ACK received address
NACK received address.
Reschedule failed transfer;
NACK received address.
Clear STO.
No action required (transfer
complete/aborted).
Acknowledge received byte;
Read SMB0DAT.
NACK received byte.
Abort failed transfer.
Reschedule failed transfer.
Abort failed transfer.
Reschedule failed transfer.
Abort failed transfer.
Reschedule failed transfer.
Values to
Write
0 0 X 0001
0 0 X 0100
0 0 X 0001
0 0 X
0 0 1
0 0 1
0 0 0
0 0 1
0 0 1
0 0 0
1 0 0
0 0 X
0 0 0
0 0 1
0 0 0
0 0 X
1 0 X
0 0 X
1 0 X
0 0 0
1 0 0
0000
0100
0000
0100
0000
1110
1110
1110
1110
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