C8051F705-GQ Silicon Laboratories Inc, C8051F705-GQ Datasheet - Page 219
![IC 8051 MCU 15K FLASH 48-TQFP](/photos/12/17/121724/c8051f705-gq_sml.jpg)
C8051F705-GQ
Manufacturer Part Number
C8051F705-GQ
Description
IC 8051 MCU 15K FLASH 48-TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F70xr
Specifications of C8051F705-GQ
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
15KB (15K x 8)
Program Memory Type
FLASH
Eeprom Size
32 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
For Use With
336-1635 - DEV KIT FOR C8051F700
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1613
Available stocks
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Quantity
Price
Company:
Part Number:
C8051F705-GQ
Manufacturer:
TI/NSC
Quantity:
210
Company:
Part Number:
C8051F705-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
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30. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by
software (i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block dia-
gram of the SMBus peripheral and the associated SFRs is shown in Figure 30.1.
S
V
L
6
M
A
S
T
E
R
Interrupt
Request
S
V
L
5
M
O
D
T
X
E
SMB0ADR
S
V
L
4
SMB0CN
S
T
A
S
L
V
3
S
O
T
S
V
L
2
Q
A
C
K
R
S
L
V
1
A
R
B
O
S
L
T
S
V
L
0
C
A
K
G
C
S
I
S
V
M
L
6
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
SDA Control
Hardware Slave Address Recognition
Hardware ACK Generation
IRQ Generation
M
SMBUS CONTROL LOGIC
S
L
V
5
SMB0ADM
M
S
V
L
4
M
S
L
V
3
M
S
V
L
2
M
E
N
S
B
Figure 30.1. SMBus Block Diagram
M
S
L
V
1
N
H
I
M
S
V
L
0
SMB0CF
B
U
S
Y
E
H
A
C
K
E
X
H
O
D
T
L
M
O
S
B
T
E
M
S
B
F
T
E
M
C
S
B
S
1
7
M
S
B
C
S
0
6
Data Path
SMB0DAT
5
Control
4
3
Rev. 1.0
2
1
0
00
01
10
11
Control
SDA
Control
SCL
T0 Overflow
T1 Overflow
TMR2H Overflow
TMR2L Overflow
FILTER
FILTER
2
N
N
C serial bus. Reads and writes to
C8051F70x/71x
SDA
SCL
C
R
O
S
S
B
A
R
Port I/O
219
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