C8051F707-GQ Silicon Laboratories Inc, C8051F707-GQ Datasheet - Page 42
![IC 8051 MCU 16K FLASH 48-TQFP](/photos/12/17/121725/c8051f707-gq_sml.jpg)
C8051F707-GQ
Manufacturer Part Number
C8051F707-GQ
Description
IC 8051 MCU 16K FLASH 48-TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F70xr
Specifications of C8051F707-GQ
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
For Use With
336-1635 - DEV KIT FOR C8051F700
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1638
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F707-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F707-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
- Current page: 42 of 306
- Download datasheet (2Mb)
C8051F70x/71x
42
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
9. A 3x3 array of 1.20 mm square openings on 1.40 mm pitch should be used for the center ground pad.
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
based on a Fabrication Allowance of 0.05 mm.
to be 60 µm minimum, all the way around the pad.
paste release.
Dimension
C1
C2
X1
X2
Y1
Y2
e
Table 6.2. QFN-48 PCB Land Pattern Dimensions
Figure 6.2. QFN-48 PCB Land Pattern
Rev. 1.0
6.80
6.80
0.20
4.00
0.75
4.00
Min
0.50 BSC
Max
6.90
6.90
0.30
4.10
0.85
4.10
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