C8051F502-IQ Silicon Laboratories Inc, C8051F502-IQ Datasheet - Page 260
![IC 8051 MCU 64K FLASH 32-QFP](/photos/12/17/121746/c8051f502-iq_sml.jpg)
C8051F502-IQ
Manufacturer Part Number
C8051F502-IQ
Description
IC 8051 MCU 64K FLASH 32-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Datasheets
1.C8051F507-IM.pdf
(312 pages)
2.C8051F502-IM.pdf
(1 pages)
3.C8051F503-IM.pdf
(312 pages)
Specifications of C8051F502-IQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
32-QFP
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1559 - KIT REF DESIGN CAN DIAGNOSTIC336-1532 - ADAPTER PROG TOOLSTICK F502336-1531 - PLATFORM PROG TOOLSTCK F502336-1528 - DAUGHTER CARD TOOLSTICK F500336-1527 - KIT DEV FOR C8051F50X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1514
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F502-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F502-IQR
Manufacturer:
RUBYCON
Quantity:
20 000
Company:
Part Number:
C8051F502-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
- Current page: 260 of 312
- Download datasheet (3Mb)
C8051F50x-F51x
SFR Definition 25.2. SPI0CN: SPI0 Control
SFR Address = 0xF8; Bit-Addressable; SFR Page = 0x00
260
Name
Reset
3:2
Bit
Type
7
6
5
4
1
0
Bit
NSSMD[1:0]
RXOVRN
TXBMT
WCOL
SPIEN
MODF
Name
SPIF
SPIF
R/W
7
0
SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are
enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service rou-
tine. This bit is not automatically cleared by hardware. It must be cleared by soft-
ware.
Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a
write to the SPI0 data register was attempted while a data transfer was in progress.
It must be cleared by software.
Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a mas-
ter mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01).
This bit is not automatically cleared by hardware. It must be cleared by software.
Receive Overrun Flag (valid in slave mode only).
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the
receive buffer still holds unread data from a previous transfer and the last bit of the
current transfer is shifted into the SPI0 shift register. This bit is not automatically
cleared by hardware. It must be cleared by software.
Slave Select Mode.
Selects between the following NSS operation modes:
(See Section 25.2 and Section 25.3).
00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the
device and will assume the value of NSSMD0.
Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer.
When data in the transmit buffer is transferred to the SPI shift register, this bit will
be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
SPI0 Enable.
0: SPI disabled.
1: SPI enabled.
WCOL
R/W
6
0
MODF
R/W
5
0
RXOVRN
R/W
Rev. 1.1
4
0
Function
3
NSSMD[1:0]
0
R/W
2
1
TXBMT
R
1
1
SPIEN
R/W
0
0
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