C8051F368-GQ Silicon Laboratories Inc, C8051F368-GQ Datasheet - Page 89
C8051F368-GQ
Manufacturer Part Number
C8051F368-GQ
Description
IC 8051 MCU 16K FLASH 32-LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Specifications of C8051F368-GQ
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
29
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
29
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 21 Channel
On-chip Dac
10 bit, 1 Channel
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
336-1650
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Price
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Part Number:
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Manufacturer:
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Quantity:
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Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using
the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFR0CN). This
function defaults to ‘enabled’ upon reset. In this way, the autoswitching function will be enabled unless dis-
abled in software.
A summary of the SFR locations (address and SFR page) is provided in Table 9.2. in the form of an SFR
memory map. Each memory location in the map has an SFR page row, denoting the page in which that
SFR resides. Note that certain SFR’s are accessible from ALL SFR pages, and are denoted by the back-
ground shading in the table. For example, the Port I/O registers P0, P1, P2, and P3 all have a shaded
background, indicating these SFR’s are accessible from all SFR pages regardless of the SFRPAGE regis-
ter value.
CIP-51
Interrupt
Logic
Figure 9.3. SFR Page Stack
SFRPGCN Bit
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
SFRPAGE
SFRNEXT
SFRLAST
89
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