C8051F364-GQ Silicon Laboratories Inc, C8051F364-GQ Datasheet - Page 123
C8051F364-GQ
Manufacturer Part Number
C8051F364-GQ
Description
IC 8051 MCU 32K FLASH 32-LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Specifications of C8051F364-GQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
29
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
29
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1646
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Bits 7–4: UNUSED: Read = 0000b, Write = don’t care.
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Note:
Bits 7–0: High Byte (bits 15–8) of MAC0 A Register.
SFR Page:
SFR Address:
SFR Page:
SFR Address:
Bit7
Bit7
R
–
R
MAC0HO: Hard Overflow Flag.
This bit is set to ‘1’ whenever an overflow out of the MAC0OVR register occurs during a
MAC operation (i.e. when MAC0OVR changes from 0x7F to 0x80 or from 0x80 to 0x7F).
The hard overflow flag must be cleared in software by directly writing it to ‘0’, or by resetting
the MAC logic using the MAC0CA bit in register MAC0CF.
MAC0Z: Zero Flag.
This bit is set to ‘1’ if a MAC0 operation results in an Accumulator value of zero. If the result
is non-zero, this bit will be cleared to ‘0’.
MAC0SO: Soft Overflow Flag.
This bit is set to ‘1’ when a MAC operation causes an overflow into the sign bit (bit 31) of the
MAC0 Accumulator. If the overflow condition is corrected after a subsequent MAC operation,
this bit is cleared to ‘0’.
MAC0N: Negative Flag.
If the MAC Accumulator result is negative, this bit will be set to ‘1’. If the result is positive or
zero, this flag will be cleared to ‘0’.
The contents of this register should not be changed by software during the first two MAC0 pipeline
stages.
0
0xCF
0
0xA5
Bit6
Bit6
R
–
R
SFR Definition 11.3. MAC0AH: MAC0 A High Byte
SFR Definition 11.2. MAC0STA: MAC0 Status
Bit5
Bit5
R
–
R
Bit4
Bit4
R
R
–
MAC0HO
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
R/W
Bit3
Bit3
R
MAC0Z
R/W
Bit2
Bit2
R
MAC0SO
R/W
Bit1
Bit1
R
MAC0N 00000100
R/W
Bit0
Bit0
R
Addressable
00000000
Reset Value
Reset Value
Bit
123
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