C8051F34B-GQ Silicon Laboratories Inc, C8051F34B-GQ Datasheet - Page 236
![IC 8051 MCU 32K FLASH 32LQFP](/photos/12/18/121852/c8051f34b-gq_sml.jpg)
C8051F34B-GQ
Manufacturer Part Number
C8051F34B-GQ
Description
IC 8051 MCU 32K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Datasheet
1.C8051F349-GQ.pdf
(276 pages)
Specifications of C8051F34B-GQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2.25 KB
Interface Type
I2C/SMBus/SPI/UART/USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
Package
32LQFP
Device Core
8051
Family Name
C8051F34x
Maximum Speed
48 MHz
Operating Supply Voltage
3.3|5 V
On-chip Adc
17-chx10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1534
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F34B-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F34B-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to
“15.1. Priority Crossbar Decoder” on page 144
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 21.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
INT0 is active as defined by bit IN0PL in register INT01CF (see SFR Definition 9.13). Setting GATE0 to ‘1’
allows the timer to be controlled by the external input signal INT0 (see
Descriptions” on page 90
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register INT01CF (see
SFR Definition 9.13).
21.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
236
INT0
T0
Crossbar
Pre-scaled Clock
SYSCLK
IN0PL
TR0
GATE0
), facilitating pulse width measurements.
0
1
1
1
X = Don't Care
Figure 21.1. T0 Mode 0 Block Diagram
XOR
TR0
0
1
GATE0
M
H
T
3
M
T
3
L
CKCON
X
M
H
0
1
1
T
2
M
T
2
L
0
1
M
T
1
M
T
0
S
C
A
1
S
C
A
0
Rev. 1.3
for information on selecting and configuring external I/O
G
A
T
E
1
C
T
1
/
INT0
M
T
1
1
TMOD
X
X
0
1
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 bits)
TL0
N
1
P
L
I
Counter/Timer
N
S
1
L
2
I
INT01CF
N
S
1
L
1
I
Disabled
Disabled
Enabled
Enabled
N
1
S
L
0
Section “9.3.5. Interrupt Register
I
N
P
0
L
(8 bits)
I
TH0
N
0
S
L
2
I
N
0
S
L
1
I
N
S
0
L
0
I
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Section
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