C8051F133-GQ Silicon Laboratories Inc, C8051F133-GQ Datasheet - Page 188

• Manufacturer Part Number: C8051F133-GQ
• Description: IC 8051 MCU 64K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F13xr

Specifications of C8051F133-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• No. Of I/o's: 32
• Ram Memory Size: 8448Byte
• Cpu Speed: 100MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1235

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
188
Bits 7–6: Reserved.
Bits 5–4: CLKDIV1–0: Output SYSCLK Divide Factor.
Bits 3–2: Reserved.
Bits 1–0: CLKSL1–0: System Clock Source Select Bits.
R/W
Bit7
-
These bits can be used to pre-divide SYSCLK before it is output to a port pin through the
crossbar.
00: Output will be SYSCLK.
01: Output will be SYSCLK/2.
10: Output will be SYSCLK/4.
11: Output will be SYSCLK/8.
See
put to a port pin.
00: SYSCLK derived from the Internal Oscillator, and scaled as per the IFCN bits in
OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the PLL.
11: Reserved.
Section “18. Port Input/Output” on page 235
R/W
Bit6
SFR Definition 14.3. CLKSEL: System Clock Selection
-
CLKDIV1 CLKDIV0
R/W
Bit5
R/W
Bit4
Rev. 1.4
R/W
Bit3
-
R/W
Bit2
-
for more details about routing this out-
CLKSL1
R/W
Bit1
SFR Address:
CLKSL0 00000000
SFR Page:
R/W
Bit0
0x97
F
Reset Value