C8051F124-GQ Silicon Laboratories Inc, C8051F124-GQ Datasheet - Page 44

• Manufacturer Part Number: C8051F124-GQ
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F124-GQ

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 8-bit or 8-ch x 12-bit
• On-chip Dac: 2-ch x 12-bit
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F12x
• Maximum Speed: 50 MHz
• No. Of I/o's: 64
• Ram Memory Size: 8448Byte
• Cpu Speed: 50MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1228

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
44
AIN2.2/A10/P1.2
AIN2.3/A11/P1.3
AIN2.4/A12/P1.4
AIN2.5/A13/P1.5
AIN2.6/A14/P1.6
AIN2.7/A15/P1.7
A10m/A2/P2.2
A11m/A3/P2.3
A12m/A4/P2.4
A13m/A5/P2.5
A14m/A6/P2.6
A15m/A7/P2.7
A8m/A0/P2.0
A9m/A1/P2.1
Name
‘F120
‘F122
‘F124
‘F126
34
33
32
31
30
29
46
45
44
43
42
41
40
39
Pin Numbers
‘F121
‘F123
‘F125
‘F127
27
26
23
22
21
20
37
36
35
34
33
32
31
30
Table 4.1. Pin Definitions (Continued)
‘F130
‘F132
34
33
32
31
30
29
46
45
44
43
42
41
40
39
‘F131
‘F133
27
26
23
22
21
20
37
36
35
34
33
32
31
30
Rev. 1.4
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O Bit 8 External Memory Address bus (Multiplexed
D I/O Port 2.1. See Port Input/Output section for com-
D I/O Port 2.2. See Port Input/Output section for com-
D I/O Port 2.3. See Port Input/Output section for com-
D I/O Port 2.4. See Port Input/Output section for com-
D I/O Port 2.5. See Port Input/Output section for com-
D I/O Port 2.6. See Port Input/Output section for com-
D I/O Port 2.7. See Port Input/Output section for com-
Type
A In
A In
A In
A In
A In
A In
Port 1.2. See Port Input/Output section for com-
plete description.
Port 1.3. See Port Input/Output section for com-
plete description.
Port 1.4. See Port Input/Output section for com-
plete description.
Port 1.5. See Port Input/Output section for com-
plete description.
Port 1.6. See Port Input/Output section for com-
plete description.
Port 1.7. See Port Input/Output section for com-
plete description.
mode)
Bit 0 External Memory Address bus (Non-multi-
plexed mode)
Port 2.0
See Port Input/Output section for complete
description.
plete description.
plete description.
plete description.
plete description.
plete description.
plete description.
plete description.
Description