PIC12F629-I/MF Microchip Technology, PIC12F629-I/MF Datasheet - Page 23

• Manufacturer Part Number: PIC12F629-I/MF
• Description: IC MCU CMOS 8BIT 1K FLASH 8-DFN
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F629-I/MF

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DFN
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNXLT08DFN - SOCKET TRANSITION ICE 8DFNAC164032 - ADAPTER PICSTART PLUS 8DFN/DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

3.2.2
Each of the GPIO pins is individually configurable as an
interrupt-on-change pin. Control bits IOC enable or
disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR'd
together to set, the GP Port Change Interrupt flag bit
(GPIF) in the INTCON register.
REGISTER 3-4:
© 2007 Microchip Technology Inc.
bit 7-6
bit 5-0
INTERRUPT-ON-CHANGE
IOC — INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)
bit 7
Unimplemented: Read as ‘0’
IOC<5:0>: Interrupt-on-Change GPIO Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be
Legend:
R = Readable bit
- n = Value at POR
U-0
—
recognized.
U-0
—
R/W-0
IOC5
W = Writable bit
’1’ = Bit is set
R/W-0
IOC4
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared.
Note:
Any read or write of GPIO. This will end the
mismatch condition.
Clear the flag bit GPIF.
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
IOC3
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF inter-
rupt flag may not get set.
PIC12F629/675
R/W-0
IOC2
x = Bit is unknown
R/W-0
IOC1
DS41190E-page 21
R/W-0
IOC0
bit 0