PIC12F675-I/MF Microchip Technology, PIC12F675-I/MF Datasheet
PIC12F675-I/MF
Specifications of PIC12F675-I/MF
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PIC12F675-I/MF Summary of contents
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... Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. © 2007 Microchip Technology Inc. PIC12F629/675 Data Sheet 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers DS41190E ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... One analog comparator - Programmable on-chip comparator voltage reference (CV - Programmable input multiplexing from device inputs - Comparator output is externally accessible • Analog-to-Digital Converter module (PIC12F675): - 10-bit resolution - Programmable 4-channel input - Voltage reference input • Timer0: 8-bit timer/counter with 8-bit programmable prescaler • Enhanced Timer1: ...
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... PIC12F629/675 Pin Diagrams 8-pin PDIP, SOIC, DFN-S GP5/T1CKI/OSC1/CLKIN GP4/T1G/OSC2/CLKOUT GP3/MCLR/V GP5/T1CKI/OSC1/CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP3/MCLR/V DS41190E-page GP0/CIN+/ICSPDAT 2 7 GP1/CIN-/ICSPCLK GP2/T0CKI/INT/COUT GP0/AN0/CIN+/ICSPDAT GP1/AN1/CIN-/V REF 4 5 GP2/AN2/T0CKI/INT/COUT PP /ICSPCLK © 2007 Microchip Technology Inc. ...
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... GPIO Port ................................................................................................................................................................................. 19 4.0 Timer0 Module .......................................................................................................................................................................... 27 5.0 Timer1 Module with Gate Control ............................................................................................................................................. 30 6.0 Comparator Module .................................................................................................................................................................. 35 7.0 Analog-to-Digital Converter (A/D) Module (PIC12F675 only) ................................................................................................... 41 8.0 Data EEPROM Memory ............................................................................................................................................................ 47 9.0 Special Features of the CPU .................................................................................................................................................... 51 10.0 Instruction Set Summary ........................................................................................................................................................... 69 11.0 Development Support ............................................................................................................................................................... 77 12.0 Electrical Specifications ............................................................................................................................................................ 81 13.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 103 14 ...
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... PIC12F629/675 NOTES: DS41190E-page 4 © 2007 Microchip Technology Inc. ...
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... The PIC12F629 and PIC12F675 devices are covered by this Data Sheet. They are identical, except the PIC12F675 has a 10-bit A/D converter. They come in 8-pin PDIP, SOIC, and MLF-S packages. Figure 1-1 shows a block diagram of the PIC12F629/675 devices. Table 1-1 shows the Pinout Description. ...
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... T1G OSC2 CLKOUT GP5/T1CKI/OSC1/CLKIN GP5 T1CKI OSC1 CLKIN Legend: Shade = PIC12F675 only TTL = TTL input buffer Schmitt Trigger input buffer DS41190E-page 6 Input Output Type Type TTL CMOS Bi-directional I/O w/ programmable pull-up and interrupt-on-change AN A/D Channel 0 input AN Comparator input TTL CMOS Serial programming I/O ...
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... Stack Level 8 RESET Vector Interrupt Vector On-chip Program Memory © 2007 Microchip Technology Inc. 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose regis- ters and the Special Function registers. The Special Function registers are located in the first 32 locations of each bank ...
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... ANSEL 20h General Purpose accesses Registers 20h-5Fh 64 Bytes 5Fh 60h 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as '0'. 1: Not a physical register. 2: PIC12F675 only. © 2007 Microchip Technology Inc. File Address (1) 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h ...
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... VCFG Legend: — = unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: This is not a physical register. 2: These bits are reserved and should always be maintained as ‘0’. 3: PIC12F675 only. © 2007 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 ...
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... ANSEL — ADCS2 Legend: — = unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: This is not a physical register. 2: These bits are reserved and should always be maintained as ‘0’. 3: PIC12F675 only. DS41190E-page 10 Bit 5 Bit 4 Bit 3 Bit 2 T0CS T0SE ...
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... Legend Readable bit - n = Value at POR © 2007 Microchip Technology Inc recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any STATUS bits. For other instructions not affecting any STATUS bits, see the “ ...
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... PSA bit to ‘1’ (OPTION<3>). See Section 4.4. R/W-1 R/W-1 R/W-1 R/W-1 T0CS T0SE PSA 128 256 1 : 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on RESET and should be initialized before clearing T0IF bit. Legend Readable bit - n = Value at POR © 2007 Microchip Technology Inc. PIC12F629/675 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit (PIC12F675 only Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt bit 5-4 Unimplemented: Read as ‘0’ ...
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... EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software The write operation has not completed or has not been started bit 6 ADIF: A/D Converter Interrupt Flag bit (PIC12F675 only The A/D conversion is complete (must be cleared in software The A/D conversion is not complete bit 5-4 Unimplemented: Read as ‘ ...
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... CAL3 CAL2 CAL1 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared U-0 R/W-0 R/W-x — POR BOD bit Bit is unknown R/W-0 U-0 U-0 CAL0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note “Implementing a Table Read" (AN556). © 2007 Microchip Technology Inc. PIC12F629/675 2.3.2 STACK The PIC12F629/675 family has an 8-level deep x 13-bit wide hardware stack (see Figure 2-1) ...
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... Not Used Bank 1 Bank 2 Bank 3 INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue Indirect Addressing ( FSR Register Location Select 1FFh © 2007 Microchip Technology Inc. ...
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... Note: The ANSEL (9Fh) and CMCON (19h) registers (9Fh) must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. The ANSEL register is defined for the PIC12F675. EXAMPLE 3-1: BCF STATUS,RP0 CLRF GPIO MOVLW ...
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... WPU5 WPU4 — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-x R/W-x R/W-x TRISIO2 TRISIO1 TRISIO0 bit Bit is unknown R/W-1 R/W-1 R/W-1 WPU2 WPU1 WPU0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be recognized. Legend Readable bit - n = Value at POR © 2007 Microchip Technology Inc. This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of GPIO ...
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... Figure 3-1 shows the diagram for this pin. The GP1 pin is configurable to function as one of the following: • general purpose I/O • an analog input for the A/D (PIC12F675 only) • an analog input to the comparator • a voltage reference input for the A/D (PIC12F675 only) DS41190E-page 22 FIGURE 3-1: BLOCK DIAGRAM OF GP0 ...
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... Figure 3-2 shows the diagram for this pin. The GP2 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D (PIC12F675 only) • the clock input for TMR0 • an external edge triggered interrupt • a digital output from the comparator ...
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... GP4/AN3/T1G/OSC2/CLKOUT Figure 3-4 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D (PIC12F675 only) • a TMR1 gate input • a crystal/resonator connection • a clock output FIGURE 3-4: ...
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... WPU — — 96h IOC — — 9Fh ANSEL — ADCS2 Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by GPIO. © 2007 Microchip Technology Inc. PIC12F629/675 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 GP5 GP4 GP3 GP2 GP1 T0IE ...
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... PIC12F629/675 NOTES: DS41190E-page 26 © 2007 Microchip Technology Inc. ...
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... Watchdog Timer WDTE Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register. © 2007 Microchip Technology Inc. Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin GP2/T0CKI. The incrementing edge is determined ...
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... Note: The ANSEL (9Fh) and CMCON (19h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. The ANSEL register is defined for the (and OSC PIC12F675. R/W-1 R/W-1 R/W-1 T0CS T0SE PSA ...
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... OPTION_REG GPPU INTEDG 85h TRISIO — — Legend: — = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2007 Microchip Technology Inc. PIC12F629/675 EXAMPLE 4-1: bcf STATUS,RP0 clrwdt clrf TMR0 bsf STATUS,RP0 movlw b’ ...
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... Timer1 module. Note: Additional information on timer modules is available in the PIC ence Manual, (DS33023). 0 TMR1L 1 T1SYNC 1 Prescaler OSC Internal 0 Clock 2 T1CKPS<1:0> TMR1CS ® Mid-Range Refer- TMR1ON TMR1GE T1G TMR1ON TMR1GE Synchronized Clock Input Synchronize Detect SLEEP Input © 2007 Microchip Technology Inc. ...
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... TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. © 2007 Microchip Technology Inc. PIC12F629/675 5.2 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1< ...
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... Stops Timer1 Legend Readable bit - n = Value at POR DS41190E-page 32 R/W-0 R/W-0 R/W-0 /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... The ANSEL (9Fh) and CMCON (19h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. The ANSEL register is defined for the PIC12F675. 5.4.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware) ...
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... PIC12F629/675 NOTES: DS41190E-page 34 © 2007 Microchip Technology Inc. ...
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... Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings Legend Readable bit - n = Value at POR © 2007 Microchip Technology Inc. be applied to an input of the comparator. In addition, GP2 can be configured as the comparator output. The Comparator Control Register (CMCON), shown in Register 6-1, contains the bits to control the comparator ...
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... Table 6-1. DS41190E-page 36 TABLE 6-1: OUTPUT STATE VS. INPUT CONDITIONS Input Conditions + is less > < > < FIGURE 6- Output Note: CINV bit (CMCON<4>) is clear. CINV COUT SINGLE COMPARATOR + Output – © 2007 Microchip Technology Inc. ...
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... GP2/COUT Analog Input, ports always reads ‘0’ Digital Input CIS = Comparator Input Switch (CMCON<3>) © 2007 Microchip Technology Inc. Comparator mode is changed, the comparator output level may not be valid for a specified period of time. Refer to the specifications in Section 12.0. Note: Comparator interrupts should be disabled during a Comparator mode change ...
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... TTL input specification. 2: Analog levels on any pin that is defined as a digital input, may cause the input buffer to consume more current than is specified CINV CMCON EN RESET impedance of 10 kΩ GP0/CIN+ GP1/CIN- CV REF CM2:CM0 © 2007 Microchip Technology Inc. ...
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... To minimize power consumption while in SLEEP mode, turn off the comparator, CM2:CM0 = 111, and voltage reference, VRCON<7> © 2007 Microchip Technology Inc. PIC12F629/675 The following equations determine the output voltages: VRR = 1 (low range): CV VRR = 0 (high range): CV ...
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... Value on Value on Bit 0 all other POR, BOD RESETS GPIF 0000 0000 0000 000u — TMR1IF 00-- 0--0 00-- 0--0 CM0 -0-0 0000 -0-0 0000 — TMR1IE 00-- 0--0 00-- 0--0 --11 1111 --11 1111 VR1 VR0 0-0- 0000 0-0- 0000 © 2007 Microchip Technology Inc. ...
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... The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference used in the conversion is software selectable to either voltage applied by the V DD shows the block diagram of the A/D on the PIC12F675 VCFG = 0 VCFG = 1 ADC GO/DONE ...
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... ADRESL LSB Bit 0 Unimplemented: Read as ‘0’ LSB Bit 0 10-bit A/D Result © 2007 Microchip Technology Inc. ...
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... This bit is automatically cleared by hardware when the A/D conversion has completed A/D conversion completed/not in progress bit 0 ADON: A/D Conversion STATUS bit 1 = A/D converter module is operating 0 = A/D converter is shut-off and consumes no operating current Legend Readable bit - n = Value at POR © 2007 Microchip Technology Inc. PIC12F629/675 U-0 U-0 R/W-0 R/W-0 — — CHS1 ...
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... Legend Readable bit - n = Value at POR DS41190E-page 44 R/W-0 R/W-0 R/W-1 ADCS1 ADCS0 ANS3 ( Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-1 R/W-1 R/W-1 ANS2 ANS1 ANS0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... sampling switch C = sample/hold capacitance (from DAC) HOLD © 2007 Microchip Technology Inc. is decreased, the acquisition time may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate Equation 7-1 may be used. This equation assumes ...
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... INTF GPIF 0000 0000 0000 000u — TMR1IF 00-- 0--0 00-- 0--0 xxxx xxxx uuuu uuuu GO ADON 00-- 0000 00-- 0000 --11 1111 --11 1111 — TMR1IE 00-- 0--0 00-- 0--0 xxxx xxxx uuuu uuuu ANS1 ANS0 -000 1111 -000 1111 © 2007 Microchip Technology Inc. ...
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... EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation Legend Readable bit - n = Value at POR © 2007 Microchip Technology Inc. PIC12F629/675 The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles ...
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... Data EEPROM write sequence. U-0 U-0 U-0 R/W-x — — — WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/S-0 R/S-0 WREN WR RD bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. © 2007 Microchip Technology Inc. PIC12F629/675 After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set ...
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... Bit 4 Bit 3 Bit 2 — — CMIF — — — WRERR WREN Value on all Value on Bit 1 Bit 0 other POR, BOD RESETS — TMR1IF 00-- 0--0 00-- 0--0 0000 0000 0000 0000 -000 0000 -000 0000 WR RD ---- x000 ---- q000 ---- ---- ---- ---- © 2007 Microchip Technology Inc. ...
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... Watchdog Timer (WDT) • SLEEP • Code protection • ID Locations • In-Circuit Serial Programming © 2007 Microchip Technology Inc. PIC12F629/675 The PIC12F629/675 has a Watchdog Timer that is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up ...
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... Specification for more information. R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CPD CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 (1) (2) (4) ( Writable bit U = Unimplemented bit, read as ‘0’ bit is set 0 = bit is cleared R/P-1 R/P-1 R/P-1 R/P-1 bit bit is unknown © 2007 Microchip Technology Inc. ...
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... C1 and C2 series resistor may be required for AT strip cut crystals varies with the Oscillator mode selected (Approx. value = 10 MΩ). © 2007 Microchip Technology Inc. FIGURE 9-2: Clock from External System Open Note 1: Functions as GP4 in EC Osc mode. TABLE 9-1: Mid- ® ...
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... OSCILLATOR Z Section 12.0, for information /4. OSC Calibrating the Internal Oscillator CALIBRATING THE INTERNAL OSCILLATOR STATUS, RP0 ;Bank 1 3FFh ;Get the cal value OSCCAL ;Calibrate STATUS, RP0 ;Bank 0 /4) is output on the OSC /4 can be used for test OSC © 2007 Microchip Technology Inc ...
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... Ripple Counter RC OSC Note 1: This is a separate oscillator from the INTOSC/EC oscillator. © 2007 Microchip Technology Inc. PIC12F629/675 They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different RESET situations as indicated in Table 9-4 ...
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... OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP (see BOD declines © 2007 Microchip Technology Inc. ...
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... Table 9-6 shows the RESET conditions for some special registers, while Table 9-7 shows the RESET conditions for all the registers. © 2007 Microchip Technology Inc. On any RESET (Power-on, Brown-out, Watchdog, etc.), the chip will remain in RESET until V above BV (see Figure 9-6) ...
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... uuu1 0uuu Wake-up from SLEEP PWRTE = 1 1024•T 1024•T OSC OSC — — Value on all Value on Bit 0 other POR, BOD (1) RESETS C 0001 1xxx 000q quuu BOD ---- --0x ---- --uq PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu © 2007 Microchip Technology Inc. ...
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... Comparator input changing, bit Timer1 rolling over, bit All other interrupts generating a wake-up will cause these bits RESET was due to brown-out, then bit All other RESETS will cause bit © 2007 Microchip Technology Inc. • MCLR Reset during normal operation • MCLR Reset during SLEEP • ...
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... MCLR Internal POR PWRT Time-out OST Time-out Internal RESET FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR Internal POR PWRT Time-out OST Time-out Internal RESET DS41190E-page 60 T PWRT T OST T PWRT T OST DD T PWRT T OST © 2007 Microchip Technology Inc. ): CASE CASE ...
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... External Interrupt GP2/INT • TMR0 Overflow Interrupt • GPIO Change Interrupts • Comparator Interrupt • A/D Interrupt (PIC12F675 only) • TMR1 Overflow Interrupt • EEPROM Data Write Interrupt The Interrupt Control register (INTCON) and Peripheral Interrupt register (PIR) record individual interrupt requests in flag bits ...
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... IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 TMR1IF TMR1IE CMIF CMIE ADIF (1) ADIE EEIF EEIE Note 1: PIC12F675 only. DS41190E-page 62 T0IF Wake-up (If in SLEEP mode) T0IE INTF INTE GPIF GPIE PEIE GIE © 2007 Microchip Technology Inc. Interrupt to CPU ...
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... SLEEP through GP2/INT interrupt. Note: The ANSEL (9Fh) and CMCON (19h) registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. The ANSEL register is defined for the PIC12F675. FIGURE 9-11: INT PIN INTERRUPT TIMING ...
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... WDT time-out occurs. Value on all Value on Bit 0 other POR, BOD RESETS GPIF 0000 0000 0000 000u TMR1IF 00-- 0--0 00-- 0--0 TMR1IE 00-- 0--0 00-- 0--0 instruction). During normal SLEEP instructions clear the WDT SLEEP = Min., Temperature = Max., Max. DD © 2007 Microchip Technology Inc. ...
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... SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 81h OPTION_REG GPPU INTEDG 2007h Config. bits CP BODEN MCLRE PWRTE WDTE Legend Unchanged, shaded cells are not used by the Watchdog Timer. © 2007 Microchip Technology Inc. PIC12F629/675 1 0 8-bit Prescaler PSA 8 1 PS0 - PS2 0 PSA ...
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... OST Interrupt Latency (Note 2) Processor in SLEEP PC+2 PC Inst( Dummy cycle Inst( instruction is being executed, the instruction. If the GIE bit is SLEEP is not desirable, the user SLEEP after the instruction. SLEEP 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) © 2007 Microchip Technology Inc. ...
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... On the bottom of the header is an 8-pin socket that plugs into the user’s target via the 8-pin stand-off connector. When the ICD pin on the PIC12F675-ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use ...
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... PIC12F629/675 NOTES: DS41190E-page 68 © 2007 Microchip Technology Inc. ...
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... A read operation is performed on a register even if the instruction writes to that register. © 2007 Microchip Technology Inc. PIC12F629/675 For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to GPIO ...
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... Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk ® Mid-Range MCU Family Ref- © 2007 Microchip Technology Inc. ...
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... Operation: (W) .AND. (f) → (destination) Status Affected: Z Description: AND the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. © 2007 Microchip Technology Inc. PIC12F629/675 BCF Bit Clear f Syntax: [label] BCF f,b 0 ≤ f ≤ 127 Operands: 0 ≤ b ≤ → ...
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... the result is stored back in register 'f'. DECF Decrement f Syntax: [label] DECF f,d 0 ≤ f ≤ 127 Operands: d ∈ [0,1] ( → (destination) Operation: Status Affected: Z Description: Decrement register 'f the result is stored in the W register the result is stored back in register 'f'. © 2007 Microchip Technology Inc. ...
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... Operation: ( → (destination) Status Affected: Z Description: The contents of register 'f' are incremented the result is placed in the W register the result is placed back in register 'f'. © 2007 Microchip Technology Inc. PIC12F629/675 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: ( → ...
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... Return with Literal label ] RETLW k 0 ≤ k ≤ 255 k → (W); TOS → PC None The W register is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. © 2007 Microchip Technology Inc. ...
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... The contents of register 'f' are rotated one bit to the right through the Carry Flag the result is placed in the W register the result is placed back in register 'f'. C Register f © 2007 Microchip Technology Inc. PIC12F629/675 SLEEP Syntax: [ label ] SLEEP Operands: None 00h → WDT, Operation: 0 → ...
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... Exclusive OR W with f Syntax: [label] XORWF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .XOR. (f) → (destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. © 2007 Microchip Technology Inc. f,d ...
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... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2007 Microchip Technology Inc. PIC12F629/675 11.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
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... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ® DSCs on an instruction © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC12F629/675 11.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
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... SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. © 2007 Microchip Technology Inc. ® ...
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... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: Voltage spikes below V SS Thus, a series resistor of 50-100 pulling this pin directly to V © 2007 Microchip Technology Inc. ........................................................................... -0. )...............................................................................................................± ).........................................................................................................± ∑ I ...
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... A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 12-2: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, -40°C ≤ T ≤ +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency ...
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... FIGURE 12-3: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 0°C ≤ T ≤ +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2.2 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. © 2007 Microchip Technology Inc. PIC12F629/675 Frequency (MHz) 20 DS41190E-page 83 ...
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... Min Typ† Max Units F OSC 2.0 — 5.5 V PIC12F629/675 with A/D off 2.2 — 5.5 V PIC12F675 with A/D on, 0°C to +125°C 2.5 — 5.5 V PIC12F675 with A/D on, -40°C to +125°C 3.0 — 5 4.5 — 5.5 V 1.5* — — V Device in SLEEP mode — V — ...
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... The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. © 2007 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) -40°C ≤ T ...
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... I and the additional current consumed when this DD PD ≤ +85°C for industrial Conditions Note WDT, BOD, Comparators REF and T1OSC disabled (1) WDT Current (1) BOD Current (1) Comparator Current (1) CV Current REF ( Current SC (1) A/D Current © 2007 Microchip Technology Inc. ...
Page 89
... The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. © 2007 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) -40°C ≤ T ...
Page 90
... I and the additional current consumed when this DD PD ≤ +125°C for extended Conditions Note WDT, BOD, Comparators REF and T1OSC disabled (1) WDT Current (1) BOD Current (1) Comparator Current (1) CV Current REF ( Current SC (1) A/D Current © 2007 Microchip Technology Inc. ...
Page 91
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. © 2007 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ T -40° ...
Page 92
... In XT, HS and LP modes when external clock is used to drive OSC1 pF ≤ +85°C A ≤ +125° Using EECON to read/write V = Minimum operating MIN voltage ms are violated ≤ +85°C A ≤ +85°C A ≤ +125° Minimum operating MIN voltage V ms are violated © 2007 Microchip Technology Inc. ...
Page 93
... I/O port mc MCLR Uppercase letters and their meanings Fall H High I Invalid (Hi-impedance) L Low FIGURE 12-4: LOAD CONDITIONS Load Condition 1 Pin R = 464Ω for all pins for OSC2 output © 2007 Microchip Technology Inc. T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z ...
Page 94
... INTOSC mode ns RC Osc mode ns XT Osc mode ns HS Osc mode 4/F CY OSC μs LP oscillator, T L/H duty cycle OSC ns HS oscillator, T L/H duty OSC cycle ns XT oscillator, T L/H duty cycle OSC ns LP oscillator ns XT oscillator ns HS oscillator © 2007 Microchip Technology Inc. ...
Page 95
... SLEEP start-up time These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. PIC12F629/675 Freq Min Typ† Max ...
Page 96
... T — CY OSC New Value Max Units Conditions 200 ns (Note 1) 200 ns (Note 1) 100 ns (Note 1) 100 ns (Note (Note 1) — ns (Note 1) — ns (Note 1) 150 * ns 300 ns — ns — — ns — © 2007 Microchip Technology Inc. ...
Page 97
... Watchdog Timer Reset I/O Pins FIGURE 12-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS VDD (Device in Brown-out Detect) RESET (due to BOD) Note delay only if PWRTE bit in configuration word is programmed to ‘0’. © 2007 Microchip Technology Inc. PIC12F629/675 (Device not in Brown-out Detect time-out 34 DS41190E-page 95 ...
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... TBD ms Extended Temperature — — 2.0 μs 2.025 — 2.175 V TBD — — — μs 100* — — © 2007 Microchip Technology Inc. Conditions = 5V, -40°C to +85°C = 5V, -40°C to +85°C = OSC1 period = 5V, -40°C to +85°C ≤ B (D005) VDD ...
Page 99
... TCKEZtmr1 Delay from external clock edge to timer increment * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2007 Microchip Technology Inc. PIC12F629/675 ...
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... LSb DD — V /32 — LSb DD ± 1/2 — — LSb ± 1/2* — — LSb — 2k* — — — 10* Comments V Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0) Ω μs © 2007 Microchip Technology Inc. ...
Page 101
... TABLE 12-8: PIC12F675 A/D CONVERTER CHARACTERISTICS: Param Sym Characteristic No. A01 N Resolution R A02 E Total Absolute ABS Error* A03 E Integral Error IL A04 E Differential Error DL A05 E Full Scale Range FS A06 E Offset Error OFF A07 E Gain Error GN A10 — Monotonicity A20 V Reference Voltage REF A20A ...
Page 102
... PIC12F629/675 FIGURE 12-10: PIC12F675 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 134 (T OSC Q4 A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 12-9: PIC12F675 A/D CONVERSION REQUIREMENTS ...
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... OSC Q4 A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 12-10: PIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE) Param Sym Characteristic No. 130 T A/D Clock Period AD 130 T A/D Internal RC ...
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... PIC12F629/675 NOTES: DS41190E-page 102 © 2007 Microchip Technology Inc. ...
Page 105
... FIGURE 13-2: TYPICAL I PD 3.5E-07 3.0E-07 2.5E-07 2.0E-07 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2.0 2.5 © 2007 Microchip Technology Inc. vs. V OVER TEMP (-40°C TO +25°C) DD Typical Baseline 3.5 4 4.5 V (V) DD vs. V OVER TEMP (+85°C) DD Typical Baseline ...
Page 106
... DS41190E-page 104 vs. V OVER TEMP (+125°C) DD Typical Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (-40°C TO +25°C) DD Maximum Baseline 3.5 4 4.5 V (V) DD 125 5.0 5.5 - 5.5 © 2007 Microchip Technology Inc. ...
Page 107
... FIGURE 13-6: MAXIMUM I PD 9.0E-06 8.0E-06 7.0E-06 6.0E-06 5.0E-06 4.0E-06 3.0E-06 2.0E-06 1.0E-06 0.0E+00 2.0 2.5 © 2007 Microchip Technology Inc. vs. V OVER TEMP (+85°C) DD Maximum Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (+125°C) DD Maximum Baseline ...
Page 108
... DS41190E-page 106 WITH BOD ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical BOD 4.5 V (V) DD WITH CMP ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical Comparator I PD 3.0 3.5 4.0 4.5 V ( 125 5 5.5 - 125 5.0 5.5 © 2007 Microchip Technology Inc. ...
Page 109
... FIGURE 13-10: TYPICAL I PD 3.5E-07 3.0E-07 2.5E-07 2.0E-07 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2 2.5 © 2007 Microchip Technology Inc. WITH A/D ENABLED vs. V OVER TEMP (-40°C TO +25°C) DD Typical A 3.5 4 4.5 V (V) DD WITH A/D ENABLED vs. V OVER TEMP (+85°C) DD Typical A/D I ...
Page 110
... DS41190E-page 108 WITH A/D ENABLED vs. V OVER TEMP (+125°C) DD Typical A 3.5 4 4.5 V (V) DD WITH T1 OSC ENABLED vs Typical 3.0 3.5 4.0 4.5 V (V) DD 125 5 5.5 OVER TEMP (-40°C TO +125°C), - 125 5.0 5.5 © 2007 Microchip Technology Inc. ...
Page 111
... FIGURE 13-14: TYPICAL 2.5 © 2007 Microchip Technology Inc. WITH CV ENABLED vs. V OVER TEMP (-40°C TO +125°C) REF DD Typical CV I REF PD 3 3.5 4 4.5 V (V) DD WITH WDT ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical WDT ...
Page 112
... DS41190E-page 110 = 3.5V) DD Internal Oscillator Frequency vs Temperature 0°C 25°C 85°C Temperature (°C) Internal Oscillator Frequency 3.0V 3.5V 4.0V 4.5V V (V) DD -3sigma average +3sigma 125°C WITH 0.1 μ F AND 0.01 μ -3sigma average +3sigma 5.0V 5.5V © 2007 Microchip Technology Inc. ...
Page 113
... FIGURE 13-17: TYPICAL WDT PERIOD vs 2.5 © 2007 Microchip Technology Inc. (-40 ° +125 ° WDT Time-out 3 3.5 4 4.5 V (V) DD PIC12F629/675 - 125 5 5.5 DS41190E-page 111 ...
Page 114
... PIC12F629/675 NOTES: DS41190E-page 112 © 2007 Microchip Technology Inc. ...
Page 115
... Note : In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007 Microchip Technology Inc. PIC12F629/675 Example 12F629-I /017 ...
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... A1 .015 E .290 .310 E1 .240 .250 D .348 .365 L .115 .130 c .008 .010 b1 .040 .060 b .014 .018 eB – c MAX 8 – .210 .195 – – .325 .280 .400 .150 .015 .070 .022 – .430 Microchip Technology Drawing C04-018B © 2007 Microchip Technology Inc. ...
Page 117
... Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2007 Microchip Technology Inc ...
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... N e 1.27 BSC A 0.80 A1 0.00 A3 0.20 REF D 5.00 BSC E 6.00 BSC D2 3.90 E2 2.20 b 0.35 L 0. NOTE MAX 8 0.85 1.00 0.01 0.05 4.00 4.10 2.30 2.40 0.40 0.48 0.60 0.75 – – Microchip Technology Drawing C04-122B © 2007 Microchip Technology Inc. ...
Page 119
... Revision B Added characterization graphs. Updated specifications. Added notes to indicate Microchip programmers maintain all calibration bits to factory settings and the PIC12F675 ANSEL register must be initialized to configure pins as digital I/O. Updated MLF-S package name to DFN-S. Revision C Revision D (01/2007) Updated Package Drawings; Replace PICmicro with PIC ...
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... These differences may cause this device to perform differently in your application than the earlier version of this device. © 2007 Microchip Technology Inc. ® PIC12F6XX 20 MHz 1024 bytes 10-bit 64 bytes ...
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... Acquisition Requirements ........................................... 45 Block Diagram............................................................. 41 Calculating Acquisition Time....................................... 45 Configuration and Operation....................................... 41 Effects of a RESET ..................................................... 46 Internal Sampling Switch (Rss) Impedance ................ 45 Operation During SLEEP ............................................ 46 PIC12F675 Converter Characteristics ...................... 101 Source Impedance...................................................... 45 Summary of Registers ................................................ 46 Absolute Maximum Ratings ................................................ 83 AC Characteristics Industrial and Extended .............................................. 94 Additional Pin Functions ..................................................... 19 Interrupt-on-Change.................................................... 21 Weak Pull-up ...
Page 122
... CONFIG (Configuration Word) ................................... 52 EEADR (EEPROM Address) ...................................... 47 EECON1 (EEPROM Control) ..................................... 48 EEDAT (EEPROM Data) ............................................ 47 INTCON (Interrupt Control)......................................... 13 IOC (Interrupt-on-Change GPIO)................................ 21 Maps PIC12F629 ........................................................... 8 PIC12F675 ........................................................... 8 OPTION_REG (Option) ........................................ 12, 28 OSCCAL (Oscillator Calibration) ................................ 16 PCON (Power Control) ............................................... 16 PIE1 (Peripheral Interrupt Enable 1)........................... 14 PIR1 (Peripheral Interrupt 1)....................................... 15 STATUS ..................................................................... 11 T1CON (Timer1 Control) ............................................ 32 VRCON (Voltage Reference Control) ...
Page 123
... Timer1 Module with Gate Control ....................................... 30 Timing Diagrams CLKOUT and I/O......................................................... 96 External Clock............................................................. 94 INT Pin Interrupt.......................................................... 63 PIC12F675 A/D Conversion (Normal Mode)............. 102 PIC12F675 A/D Conversion Timing (SLEEP Mode) .......................................................... 103 RESET, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ......................................... 97 Time-out Sequence on Power-up (MCLR not Tied to ...
Page 124
... PIC12F629/675 NOTES: DS41190E-page 122 © 2007 Microchip Technology Inc. ...
Page 125
... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2007 Microchip Technology Inc. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...
Page 126
... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS41190E-page 124 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS41190E © 2007 Microchip Technology Inc. ...
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... JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. © 2007 Microchip Technology Inc. XXX Examples: Pattern a) PIC12F629 package, 20 MHz, QTP pattern #301 b) PIC12F675 package, 20 MHz range DD PIC12F629/675 -E/P 301 = Extended Temp., PDIP -I/SN = Industrial Temp., SOIC DS41190E-page 125 ...
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... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...