PIC16F1827-I/SO Microchip Technology, PIC16F1827-I/SO Datasheet - Page 277

• Manufacturer Part Number: PIC16F1827-I/SO
• Description: IC PIC MCU FLASH 4K 18-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1827-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 18SOIC W
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 32 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

24.6.13.2
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
When the user releases SDAx and the pin is allowed to
float high, the BRG is loaded with SSPxADD and
counts down to zero. The SCLx pin is then deasserted
and when sampled high, the SDAx pin is sampled.
FIGURE 24-36:
FIGURE 24-37:
 2010 Microchip Technology Inc.
A low level is sampled on SDAx when SCLx
goes from low level to high level.
SCLx goes low before SDAx is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
SDAx
SCLx
BCLxIF
RSEN
S
SSPxIF
SDAx
SCLx
RSEN
BCLxIF
S
SSPxIF
Bus Collision During a Repeated
Start Condition
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SCLx goes low before SDAx,
set BCLxIF. Release SDAx and SCLx.
Preliminary
T
BRG
Sample SDAx when SCLx goes high.
If SDAx = 0, set BCLxIF and release SDAx and SCLx.
If SDAx is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 24-35).
If SDAx is sampled high, the BRG is reloaded and
begins counting. If SDAx goes from high-to-low before
the BRG times out, no bus collision occurs because no
two masters can assert SDAx at exactly the same time.
If SCLx goes from high-to-low before the BRG times
out and SDAx has not already been asserted, a bus
collision occurs. In this case, another master is
attempting to transmit a data ‘1’ during the Repeated
Start condition, see Figure 24-36.
If, at the end of the BRG time-out, both SCLx and SDAx
are still high, the SDAx pin is driven low and the BRG
is reloaded and begins counting. At the end of the
count, regardless of the status of the SCLx pin, the
SCLx pin is driven low and the Repeated Start
condition is complete.
PIC16F/LF1826/27
T
Cleared by software
BRG
Interrupt cleared
by software
’0’
’0’
DS41391C-page 277
’0’