PIC12CE518-04I/SM Microchip Technology, PIC12CE518-04I/SM Datasheet - Page 86

• Manufacturer Part Number: PIC12CE518-04I/SM
• Description: IC MCU OTP 512X12 W/EE 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12CE518-04I/SM

• Core Size: 8-Bit
• Program Memory Size: 768B (512 x 12)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Type: OTP
• Eeprom Size: 16 x 8
• Ram Size: 25 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 16Byte
• Ram Memory Size: 25Byte
• Cpu Speed: 4MHz
• No.: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PICmicro MID-RANGE MCU FAMILY
5.2
5.3
5.4
DS31005A-page 5-4
General Instruction Format
Central Processing Unit (CPU)
Instruction Clock
The Mid-Range MCU instructions can be broken down into four general formats as shown in
Figure
opcode size is what allows 35 instructions to be implemented.
Figure 5-1: General Format for Instructions
The CPU can be thought of as the “brains” of the device. It is responsible for fetching the correct
instruction for execution, decoding that instruction, and then executing that instruction.
The CPU sometimes works in conjunction with the ALU to complete the execution of the instruc-
tion (in arithmetic and logical operations).
The CPU controls the program memory address bus, the data memory address bus, and
accesses to the stack.
Each instruction cycle (T
as the device oscillator cycle time (T
Decode, Read, Process Data, Write, etc., of each instruction cycle. The following diagram shows
the relationship of the Q cycles to the instruction cycle.
The four Q cycles that make up an instruction cycle (T
Each instruction will show a detailed Q cycle operation for the instruction.
Figure 5-2: Q Cycle Activity
Bit-oriented file register operations
Byte-oriented file register operations
Literal and control operations
General
CALL and GOTO instructions only
Q1:
Q2:
Q3:
Q4:
13
13
13
13
5-1. As can be seen the opcode for the instruction varies from 3-bits to 6-bits. This variable
Tosc
OPCODE
OPCODE
OPCODE
OPCODE
Instruction Decode Cycle or forced No operation
Instruction Read Data Cycle or No operation
Process the Data
Instruction Write Data Cycle or No operation
11
Q1
10 9
10
8
Q2
CY
b (BIT #)
d
T
7
) is comprised of four Q cycles (Q1-Q4). The Q cycle time is the same
8
CY
Q3
1
6
7
7 6
k (literal)
Q4
f (FILE #)
k (literal)
OSC
f (FILE #)
Q1
). The Q cycles provide the timing/designation for the
Q2
0
0
0
0
T
CY
Q3
2
CY
) can be generalized as:
Q4
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
b = 3-bit bit address
f = 7-bit file register address
k = 8-bit immediate value
k = 11-bit immediate value
Q1
1997 Microchip Technology Inc.
Q2
T
CY
Q3
3
Q4