PIC18F44J50-I/PT Microchip Technology, PIC18F44J50-I/PT Datasheet
PIC18F44J50-I/PT
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PIC18F44J50-I/PT Summary of contents
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... PIC18LF45J11 • PIC18F46J11 • PIC18LF46J11 • PIC18F24J50 • PIC18LF24J50 • PIC18F25J50 • PIC18LF25J50 • PIC18F26J50 • PIC18LF26J50 • PIC18F44J50 • PIC18LF44J50 • PIC18F45J50 • PIC18LF45J50 • PIC18F46J50 • PIC18LF46J50 TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18F2XJXX/4XJXX FAMILY Pin Name Pin Name ...
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... OSC1 19 10 OSC2 11 18 RC0 17 12 RC1 RC2 RC3 RA2 1 21 RA3 PIC18F2XJ10 CAP 19 PIC18F2XJ11 RA5 4 18 PIC18F2XJ50 RB7/PGD RB6/PGC RB5 RB4 RB3 RB2 RB1 RB0 RC7 RC6 RC5 RC4 RB3 RB2 RB1 RB0 RC7 © 2008 Microchip Technology Inc. ...
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... QFN 44-Pin TQFP RC7 1 RD4 2 RD5 3 PIC18F4XJ10 4 RD6 RD7 5 PIC18F4XJ11 PIC18F4XJ50 RB0 8 9 RB1 10 RB2 11 RB3 © 2008 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY 1 40 RA0 2 39 RA1 3 38 RA2 4 37 RA3 CAP 6 35 RA5 7 34 RE0 8 33 RE1 9 32 RE2 ...
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... Table 2-2. The overall memory maps for all the devices are shown in Figure 2-4. pins. The TABLE 2- DDCORE CAP Device* PIC18F24J10 PIC18F44J10 PIC18F24J11 PIC18F44J11 PIC18F24J50 PIC18F44J50 PIC18F25J10 PIC18F45J10 PIC18F25J11 PIC18F45J11 PIC18F25J50 PIC18F45J50 PIC18F26J11 PIC18F46J11 PIC18F26J50 PIC18F46J50 * Includes PIC18F and PIC18LF devices. For purposes of code protection, the program memory for every device is treated as a single block ...
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... Table Pointer register, which in turn, is comprised of three registers: • TBLPTRU at RAM address 0FF8h • TBLPTRH at RAM address 0FF7h • TBLPTRL at RAM address 0FF6h © 2008 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY TBLPTRU Addr[21:16] The 4-bit command, ‘0000’ (core instruction), is used to load the Table Pointer prior to using many read or write operations ...
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... Words Configuration Space Device IDs (1) PIC18FX6JXX (64 Kbytes) 000000h Code Memory 003FFFh 007FFFh 00BFFFh Flash Conf. Words 00FFFFh Unimplemented Read as ‘0’ 1FFFFFh 200000h Configuration Space 2FFFFFh 300000h Configuration Words (2) 300007h Configuration Space 3FFFFEh Device IDs 3FFFFFh © 2008 Microchip Technology Inc. ...
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... P13 P1 MCLR V DD PGD PGC P19 © 2008 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY 2.4 Entering and Exiting ICSP™ Program/Verify Mode Entry into ICSP modes for PIC18F2XJXX/4XJXX fam- ily devices is somewhat different than previous PIC18 devices. As shown in Figure 2-6, entering ICSP Program/Verify mode requires three steps: 1 ...
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... Data Payload PGD = Input COMMANDS FOR PROGRAMMING 4-Bit Description Command 0000 0010 1000 1001 1010 1011 1100 1101 1110 1111 SAMPLE COMMAND SEQUENCE Data Core Instruction Payload 3C 40 Table Write, post-increment P5A Fetch Next 4-Bit Command © 2008 Microchip Technology Inc. ...
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... FIGURE 3-2: BULK ERASE TIMING PGC P5 PGD 4-Bit Command 16-Bit Data Payload © 2008 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY TABLE 3-1: 4-Bit Command 0000 0000 0000 0000 0000 0000 1100 0000 0000 0000 0000 0000 0000 1100 0000 0000 FIGURE 3-1: 1 ...
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... Erase a Core Instruction BSF EECON1, WREN CLRF TBLPTRU CLRF TBLPTRH CLRF TBLPTRL BSF EECON1, FREE BSF EECON1, WR NOP – hold PGC high for time P9 and low for time P10. to completely erase a family device. The timing © 2008 Microchip Technology Inc. ...
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... FIGURE 3-3: SINGLE ROW ERASE CODE MEMORY FLOW Addr = Addr + 1024 © 2008 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY Start Addr = 0 Configure Device for Row Erases Start Erase Sequence and Hold PGC High for Time P9 Hold PGC Low for Time P10 All ...
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... MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL Write 2 bytes and post-increment address by 2. Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. sequence to program necessary to completely write © 2008 Microchip Technology Inc ...
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... FIGURE 3-5: TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111 PGC P5 PGD 4-Bit Command © 2008 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> All No Bytes Written? Yes Start Write Sequence and Hold PGC ...
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... MOVWF TBLPTRL Write 2 bytes and post-increment address by 2. Repeat write operation 30 more times to fill the write buffer Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. BCF EECON1, WREN © 2008 Microchip Technology Inc. ...
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... PGD = Input © 2008 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output. During this time, PGC must be held low (see Figure 4-1). This operation also increments the Table Pointer by one, pointing to the next byte in code memory for the next read ...
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... Given that Blank Checking is merely code verification with FFh expect data, refer to Section 4.2 “Verify Code Memory and Configuration Word” for implementation details. FIGURE 4-3: Start Blank Check Device Device Blank? Abort Failure, Report Error BLANK CHECK FLOW Is Yes Continue No © 2008 Microchip Technology Inc. ...
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... The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP accidentally executed. 2: This bit should always be maintained at ‘0’. 3: DEVID registers are read-only and cannot be programmed by the user. © 2008 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY TABLE 5-1: CONFIG3L, Configuration are ...
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... CCP2MX CONFIG3H CCP2 MUX bit 1 = CCP2 is multiplexed with RC1 0 = CCP2 is multiplexed with RB3 DS39687D-page 18 Description purpose I/O pins (Legacy mode) OSCCON<1:0> © 2008 Microchip Technology Inc. ...
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... Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code protection, perform an ICSP™ Bulk Erase operation. 5: The WPFP write protection does not override CPn. Write-protect function of the two. © 2008 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY Bit 5 ...
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... Reset reloaded with the programmed value at any device Reset. DD (1) © 2008 Microchip Technology Inc. ...
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... Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code protection, perform an ICSP™ Bulk Erase operation. 5: The WPFP write protection does not override CPn. Write-protect function of the two. © 2008 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY Description Deep Sleep Watchdog Timer Postscale Select bits The DSWDT prescaler is 32 ...
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... Used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number. Revision ID bits Indicate the device revision. Device ID bits Used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number. Reset reloaded with the programmed value at any device Reset. DD © 2008 Microchip Technology Inc. ...
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... TABLE 5-6: Device PIC18F24J10 PIC18F25J10 PIC18F44J10 PIC18F45J10 PIC18LF24J10 PIC18LF25J10 PIC18LF44J10 PIC18LF45J10 PIC18F25J11 PIC18F24J11 PIC18F26J11 PIC18F45J11 PIC18F44J11 PIC18F46J11 PIC18F24J50 PIC18F25J50 PIC18F26J50 PIC18F44J50 PIC18F45J50 PIC18F46J50 PIC18LF2450 PIC18LF25J50 PIC18LF26J50 PIC18LF44J50 PIC18LF45J50 PIC18LF46J50 PIC18LF24J11 PIC18LF25J11 PIC18LF26J11 PIC18LF44J11 PIC18LF45J11 PIC18LF46J11 DEVICE ID VALUE Device ID Value DEVID2 DEVID1 ...
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... SUM[000000:003FF7] + ([003FF8] & EFh) + ([003FF9] & FFh) + Off ([003FFA] & DFh) + ([003FFB] & FFh) + ([003FFC] & FFh) + ([003FFD] & F9h) + PIC18F24J50 ([003FFE] & FFh) + ([003FFF] & F1h) PIC18F44J50 On 0000h SUM[000000:007FF7] + ([007FF8] & E1h) + ([007FF9] & 04h) + ([007FFA] & C7h) + Off PIC18F25J10 ([007FFB] & ...
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... External power must be supplied to the V Section 2.1.1 “PIC18F2XJXX/4XJXX/ LF2XJXX/LF4XJXX Devices and the On-Chip Voltage Regulator” for more information must also be supplied to the and V , respectively © 2008 Microchip Technology Inc. PIC18F2XJXX/4XJXX FAMILY Min Max 2.25 2.75 PIC18LFXXJXX V 3.60 DDCORE PIC18FXXJ10 2.70 3.60 PIC18FXXJ50/ 2 ...
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... See DDCORE CAP pins during programming. AV and Units Conditions μ μ should always be within ±0.3V SS © 2008 Microchip Technology Inc. ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...