PIC16F916-I/ML Microchip Technology, PIC16F916-I/ML Datasheet - Page 120

• Manufacturer Part Number: PIC16F916-I/ML
• Description: IC PIC MCU FLASH 8KX14 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F916-I/ML

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 352 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 24
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 352Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 352 B
• Interface Type: SSP, I2C, AUSART, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / Rohs Status: Details

PIC16F913/914/916/917/946
8.10
The Comparator Voltage Reference module provides
an internally generated voltage reference for the com-
parators. The following features are available:
• Independent from Comparator operation
• Two 16-level voltage ranges
• Output clamped to V
• Ratiometric with V
The VRCON register (Register 8-3) controls the
Voltage Reference module shown in Figure 8-8.
8.10.1
The comparator voltage reference is independent of
the comparator configuration. Setting the VREN bit of
the VRCON register will enable the voltage reference.
8.10.2
The
voltage levels in each range. Range selection is
controlled by the VRR bit of the VRCON register. The
16 levels are set with the VR<3:0> bits of the VRCON
register.
The CV
equations:
REGISTER 8-3:
DS41250F-page 118
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
R/W-0
VREN
CV
REF
REF
Comparator Voltage Reference
INDEPENDENT OPERATION
OUTPUT VOLTAGE SELECTION
output voltage is determined by the following
voltage reference has 2 ranges with 16
VREN: CV
1 = CV
0 = CV
Unimplemented: Read as ‘0’
VRR: CV
1 = Low range
0 = High range
Unimplemented: Read as ‘0’
VR<3:0>: CV
When VRR = 1: CV
When VRR = 0: CV
DD
U-0
—
VRCON: VOLTAGE REFERENCE CONTROL REGISTER
SS
REF
REF
REF
REF
circuit powered on
circuit powered down, no I
Range Selection bit
REF
W = Writable bit
‘1’ = Bit is set
Enable bit
Value Selection bits (0 ≤ VR<3:0> ≤ 15)
R/W-0
VRR
REF
REF
= (VR<3:0>/24) * V
= V
DD
/4 + (VR<3:0>/32) * V
U-0
—
DD
drain and CV
DD
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
EQUATION 8-1:
The full range of V
the construction of the module. See Figure 8-8.
8.10.3
The CV
power consumption by configuring VRCON as follows:
• VREN = 0
• VRR = 1
• VR<3:0> = 0000
This allows the comparator to detect a zero-crossing
while not consuming additional CV
8.10.4
The comparator voltage reference is V
therefore, the CV
V
Voltage Reference can be found in Section 19.0
“Electrical Specifications”.
VR3
DD
V
V
. The tested absolute accuracy of the Comparator
DD
RR
RR
REF
REF
=
=
CV
CV
0 (high range):
1 (low range):
= V
OUTPUT CLAMPED TO V
OUTPUT RATIOMETRIC TO VDD
output voltage can be set to Vss with no
REF
REF
R/W-0
SS
VR2
REF
.
=
=
SS
output changes with fluctuations in
(VR<3:0>/24)
(V
to V
CV
DD
© 2007 Microchip Technology Inc.
DD
/4) +
x = Bit is unknown
REF
cannot be realized due to
R/W-0
VR1
OUTPUT VOLTAGE
(VR<3:0> V
REF
×
V
DD
module current.
DD
×
SS
derived and
R/W-0
VR0
DD
/32)
bit 0