PIC16C433-I/P Microchip Technology, PIC16C433-I/P Datasheet - Page 66

• Manufacturer Part Number: PIC16C433-I/P
• Description: IC MCU CMOS 8BIT 10MHZ 2K 18-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C433-I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN (Local Interconnect Network)
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• For Use With: DVA16XP185 - ADAPTER DEVICE ICE 18DIP/SOICAC164030 - MODULE SKT PROMATEII 28DIP/SOICDVA16XP140 - ADAPTER DEVICE FOR MPLAB-ICE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PIC16C433
FIGURE 9-16: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 9-8:
9.8
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either V
cuitry is drawing current from the I/O pin, power-down
the A/D, and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input, if enabled, should also be at V
for lowest current consumption. The contribution from
on-chip pull-ups on GPIO should be considered.
The MCLR pin, if enabled, must be at a logic high level
(V
9.8.1
The device can wake-up from SLEEP through one of
the following events:
DS41139B-page 64
Address
2007h
81h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 9-1 for operation of these bits. Not all CP0 and CP1 bits are shown.
IHMC
Note: PSA and PS<2:0> are bits in the OPTION register.
).
Power-down Mode (SLEEP)
WAKE-UP FROM SLEEP
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Config. bits
OPTION
DD
or V
WDT Timer
Enable Bit
WDT
SS
, ensure no external cir-
(1)
From TMR0 Clock Source
(Figure 7-5)
MCLRE
GPPU
Bit 7
DD
0
1
or V
INTEDG
PSA
Bit 6
CP1
M
U
X
Preliminary
SS
,
T0CS
Bit 5
CP0
1.
2.
3.
4.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a wake-up. The TO and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT timeout occurred (and caused
wake-up).
The following peripheral interrupt can wake the device
from SLEEP:
1.
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip Q clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
0
PWRTE
External RESET input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
GP2/INT interrupt, interrupt GPIO port change
or some peripheral interrupts.
LIN bus activity (connect BACT to GP2/T0CKI/
AN2/INT pin).
A/D conversion (when A/D clock source is RC).
Timeout
8 - to - 1 MUX
MUX
T0SE
Bit 4
WDT
Postscaler
1
8
WDTE
Bit 3
PSA
PSA
To TMR0 (Figure 7-5)
 2002 Microchip Technology Inc.
FOSC2
Bit 2
PS2
PS<2:0>
FOSC1
Bit 1
PS1
FOSC0
Bit 0
PS0